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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. TPS65216 slds187 ? october 2018 TPS65216 power management for amic110 and amic120 processors 1 device overview 1 1.1 features 1 ? three adjustable step-down converters with integrated switching fets (dcdc1, dcdc2, dcdc3): ? dcdc1: 1.1-v default, up to 1.8 a ? dcdc2: 1.1-v default, up to 1.8 a ? dcdc3: 1.2-v default, up to 1.8 a ? vin range from 3.6 v to 5.5 v ? adjustable output voltage range 0.85 v to 1.675 v (dcdc1 and dcdc2) ? adjustable output voltage range 0.9 v to 3.4 v (dcdc3) ? power save mode at light load current ? 100% duty cycle for lowest dropout ? active output-discharge when disabled ? one adjustable buck-boost converter with integrated switching fets (dcdc4): ? dcdc4: 3.3 v default, up to 1.6 a ? vin range from 3.6 v to 5.5 v ? adjustable output voltage range 1.175 v to 3.4 v ? active output-discharge when disabled ? adjustable general-purpose ldo (ldo1) ? ldo1: 1.8-v default up to 400 ma ? vin range from 1.8 v to 5.5 v ? adjustable output voltage range from 0.9 v to 3.4 v ? active output-discharge when disabled ? high-voltage load switch ( ls) with 100-ma or 500-ma selectable current limit ? vin range from 1.8 v to 10 v ? 500-m (max) switch impedance ? supervisor with built-in supervisor function monitors ? dcdc1, dcdc2 4% tolerance ? dcdc3, dcdc4 5% tolerance ? ldo1 5% tolerance ? protection, diagnostics, and control: ? undervoltage lockout (uvlo) ? always-on push-button monitor ? overtemperature warning and shutdown ? i 2 c interface (address 0x24) (see timing requirements for i 2 c operation at 400 khz) 1.2 applications ? industrial automation ? electronic point of sale (epos) ? test and measurement ? personal navigation ? industrial communications ? backplane i/o ? connected industrial drives 1.3 description the TPS65216 is a single chip, power-management ic (pmic) specifically designed to support the amic110 and amic120 line of processors in line-powered (5 v) applications. the device is characterized across a ? 40 c to +105 c temperature range, making it suitable for various industrial applications. the TPS65216 is specifically designed to provide power management for all the functionalities of the amic110 and amic120 processors. the dc/dc converters dcdc1 through dcdc4 are intended to power the core, mpu, ddr memory, and 3.3-v analog and i/o, respectively. ldo1 provides the 1.8-v analog and i/o for the processor. gpio2 allows for warm reset of the dcdc1 and dcdc2 converters. the i 2 c interface allows the user to enable and disable all voltage regulators, the load switch, and gpios. additionally, uvlo and supervisor voltage thresholds, power-up sequence, and power-down sequence can be programmed through i 2 c. interrupts for overtemperature, overcurrent, and undervoltage can be monitored as well. the supervisor monitors dcdc1 through dcdc4 and ldo1. the supervisor has two settings, one for typical undervoltage tolerance (strict = 0b), and one for tight undervoltage and overvoltage tolerances (strict = 1b). a power-good signal indicates proper regulation of the five voltage regulators. ordernow productfolder support &community tools & software technical documents
2 TPS65216 slds187 ? october 2018 www.ti.com submit documentation feedback product folder links: TPS65216 device overview copyright ? 2018, texas instruments incorporated (1) for all available packages, see the orderable addendum at the end of the data sheet. three hysteretic step-down converters are targeted at providing power for the processor core, mpu, and ddrx memory. the default output voltages for each converter can be adjusted through the i 2 c interface. dcdc1 and dcdc2 feature dynamic voltage scaling to provide power at all operating points of the processor. dcdc1 and dcdc2 also have programmable slew rates to help protect processor components. dcdc3 remains powered while the processor is in a sleep mode to maintain power to ddrx memory. the TPS65216 device is available in a 48-pin vqfn package (6 mm 6 mm, 0.4-mm pitch). device information (1) part number package body size (nom) TPS65216 vqfn (48) 6.00 mm 6.00 mm
3 TPS65216 www.ti.com slds187 ? october 2018 submit documentation feedback product folder links: TPS65216 device overview copyright ? 2018, texas instruments incorporated 1.4 simplified schematic figure 1-1. simplified schematic TPS65216 in_dcdc2 fb3 pb fb1 l1 in_dcdc1 sda scl ldo1 in_ldo1 in_ls ls nc pfi dcdc4 l4b l4a pgood ac_det npfo gpio1 in_dcdc4 gnd gnd gnd gnd gnd gnd gnd nc nc gnd gpio2 gnd in_bias int_ldo nc gnd gnd in_dcdc3 l3 nwakeup fb2 l2 nint pwr_en nc dc34_sel 1.5 h 1.5 h 1.5 h 10 ? f 4.7 ? f 10 ? f 4.7 ? f 10 ? f 100 k 100 k in_bias 100 k vio 100 k 4.7 ? f 100 k vio 100 k vio 10 ? f 4.7 ? f 10 ? f 100 k vio 100 k in_bias 100 k vio 100 k vio 4.7 ? f 1.5 h 47 ? f 100 nf 1 ? f 100 k vio copyright ? 2018, texas instruments incorporated vio
4 TPS65216 slds187 ? october 2018 www.ti.com submit documentation feedback product folder links: TPS65216 table of contents copyright ? 2018, texas instruments incorporated table of contents 1 device overview ......................................... 1 1.1 features .............................................. 1 1.2 applications ........................................... 1 1.3 description ............................................ 1 1.4 simplified schematic ................................. 3 2 pin configuration and functions ..................... 5 2.1 pin functions ......................................... 5 3 specifications ............................................ 7 3.1 absolute maximum ratings .......................... 7 3.2 esd ratings .......................................... 7 3.3 recommended operating conditions ................ 8 3.4 thermal information .................................. 8 3.5 electrical characteristics ............................. 9 3.6 timing requirements ............................... 15 3.7 typical characteristics .............................. 17 4 detailed description ................................... 18 4.1 overview ............................................ 18 4.2 functional block diagram ........................... 19 4.3 feature description ................................. 20 4.4 device functional modes ........................... 38 4.5 register maps ....................................... 40 5 application and implementation .................... 81 5.1 application information .............................. 81 5.2 typical application .................................. 82 6 power supply recommendations .................. 85 7 layout .................................................... 85 7.1 layout guidelines ................................... 85 7.2 layout example ..................................... 86 8 device and documentation support ............... 87 8.1 device support ...................................... 87 8.2 documentation support ............................. 87 8.3 receiving notification of documentation updates .. 87 8.4 community resources .............................. 87 8.5 trademarks .......................................... 87 8.6 electrostatic discharge caution ..................... 88 8.7 glossary ............................................. 88 9 mechanical, packaging, and orderable information .............................................. 88 9.1 package option addendum ......................... 89
5 TPS65216 www.ti.com slds187 ? october 2018 submit documentation feedback product folder links: TPS65216 pin configuration and functions copyright ? 2018, texas instruments incorporated 2 pin configuration and functions figure 2-1 shows the 48-pin rsl plastic quad flatpack no-lead. figure 2-1. 48-pin rsl vqfn with exposed thermal pad (top view, 6 mm 6 mm 1 mm with 0.4-mm pitch) 2.1 pin functions pin functions pin type description no. name 1 in_dcdc1 p input supply pin for dcdc1. 2 sda i/o data line for the i 2 c interface. connect to pullup resistor. 3 scl i clock input for the i 2 c interface. connect to pullup resistor. 4 ldo1 o output voltage pin for ldo1. connect to capacitor. 5 in_ldo1 p input supply pin for ldo1. 6 in_ls p input supply pin for the load switch. 7 ls o output voltage pin for the load switch. connect to capacitor. 8 pgood o power-good output (configured as open drain). pulled low when either dcdc1-4 or ldo1 are out of regulation. load switch does not affect pgood pin. 9 ac_det i ac monitor input and enable for dcdc1-4, ldo1 and load switch. see section 4.4.1 for details. tie pin to in_bias if not used. 48 l1 13 l4a 1 in_dcdc1 36 in_bias 47 fb1 14 l4b 2 sda 35 int_ldo 46 pwr_en 15 dcdc4 3 scl 34 n/c 45 nint 16 pfi 4 ldo1 33 gnd 44 pb 17 dc34_sel 5 in_ldo1 32 gnd 43 in_dcdc2 18 n/c 6 in_ls 31 gnd 42 l2 19 n/c 7 ls 30 gnd 41 fb2 20 gnd 8 pgood 29 n/c 40 nwakeup 21 gnd 9 ac_det 28 n/c 39 fb3 22 gnd 10 npfo 27 gnd 38 l3 23 gnd 11 gpio1 26 gpio2 37 in_dcdc3 24 gnd 12 in_dcdc4 25 gnd not to scale thermal pad
6 TPS65216 slds187 ? october 2018 www.ti.com submit documentation feedback product folder links: TPS65216 pin configuration and functions copyright ? 2018, texas instruments incorporated pin functions (continued) pin type description no. name 10 npfo o power-fail comparator output, deglitched (open drain). pin is pulled low when pfi input is below power-fail threshold. 11 gpio1 i/o general-purpose, open-drain output. see section 4.3.1.11 for more information. 12 in_dcdc4 p input supply pin for dcdc4. 13 l4a p switch pin for dcdc4. connect to inductor. 14 l4b p switch pin for dcdc4. connect to inductor. 15 dcdc4 p output voltage pin for dcdc4. connect to capacitor. 16 pfi i power-fail comparator input. connect to resistor divider. 17 dc34_sel i power-up default selection pin for dcdc3 or dcdc4. power-up default is programmed by a resistor connected to ground. see section 4.3.1.10 for resistor options. 18 n/c ? no connect. leave pin floating. 19 n/c ? no connect. leave pin floating. 20 gnd ? connect pin to ground. 21 gnd 22 gnd 23 gnd 24 gnd 25 gnd 26 gpio2 i/o pin can be configured as warm reset (negative edge) for dcdc1/2 or as a general-purpose, open-drain output. see section 4.3.1.11 for more details. 27 gnd ? connect pin to ground. 28 n/c ? no connect. leave pin floating. 29 n/c 30 gnd ? connect pin to ground. 31 gnd 32 gnd 33 gnd 34 n/c ? no connect. leave pin floating. 35 int_ldo p internal bias voltage. connect to a 1- f capacitor. ti does not recommended connecting any external load to this pin. 36 in_bias p input supply pin for reference system. 37 in_dcdc3 p input supply pin for dcdc3. 38 l3 p switch pin for dcdc3. connect to inductor. 39 fb3 i feedback voltage pin for dcdc3. connect to output capacitor. 40 nwakeup o signal to soc to indicate a power on event (active low, open-drain output). 41 fb2 i feedback voltage pin for dcdc2. connect to output capacitor. 42 l2 p switch pin for dcdc2. connect to inductor. 43 in_dcdc2 p input supply pin for dcdc2. 44 pb i push-button monitor input. typically connected to a momentary switch to ground (active low). see section 4.4.1 for details. 45 nint o interrupt output (active low, open drain). pin is pulled low if an interrupt bit is set. the pin returns to hi-z state after the bit causing the interrupt has been read. interrupts can be masked. 46 pwr_en i power enable input for dcdc1-4, ldo1 and load switch. see section 4.4.1 for details. 47 fb1 i feedback voltage pin for dcdc1. connect to output capacitor. 48 l1 p switch pin for dcdc1. connect to inductor. ? thermal pad p power ground and thermal relief. connect to ground plane.
7 TPS65216 www.ti.com slds187 ? october 2018 submit documentation feedback product folder links: TPS65216 specifications copyright ? 2018, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 3 specifications 3.1 absolute maximum ratings operating under free-air temperature range (unless otherwise noted) (1) min max unit supply voltage in_bias, in_ldo1, in_dcdc1, in_dcdc2, in_dcdc3, in_dcdc4 ? 0.3 7 v in_ls ? 0.3 11.2 input voltage all pins unless specified separately ? 0.3 7 v output voltage all pins unless specified separately ? 0.3 7 v sink current pgood, nwakeup, nint, npfo, sda, gpio1, gpio2 6 ma t a operating ambient temperature ? 40 105 c t j junction temperature ? 40 125 c t stg storage temperature ? 65 150 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 3.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm), per ansi/esda/jedec js-001 (1) 2000 v charged-device model (cdm), per jedec specification jesd22-c101 (2) 500
8 TPS65216 slds187 ? october 2018 www.ti.com submit documentation feedback product folder links: TPS65216 specifications copyright ? 2018, texas instruments incorporated 3.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) min nom max unit supply voltage, in_bias 3.6 5.5 v input voltage for dcdc1, dcdc2, dcdc3, dcdc4 3.6 5.5 v input voltage for ldo1 1.8 5.5 v input voltage for ls 1.8 10 v output voltage for dcdc1 0.85 1.675 v output voltage for dcdc2 0.85 1.675 v output voltage for dcdc3 0.9 3.4 v output voltage for dcdc4 1.175 3.4 v output voltage for ldo1 0.9 3.4 v output current for dcdc1, dcdc2, dcdc3 0 1.8 a output current for dcdc4 vin_dcdc4 = 2.8 v 1 a vin_dcdc4 = 3.6 v 1.3 vin_dcdc4 = 5 v 1.6 output current for ldo1 0 400 ma output current for ls vin_ls > 2.3 v 0 900 ma vin_ls 2.3 v 0 475 (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report. 3.4 thermal information thermal metric (1) TPS65216 unit rsl (vqfn) 16 pins r jc(top) junction-to-case (top) 17.2 c/w r jb junction-to-board 5.8 c/w r ja thermal resistance, junction to ambient. jedec 4-layer, high-k board. 30.6 c/w jt junction-to-package top 0.2 c/w jb junction-to-board 5.6 c/w r jc(bot) junction-to-case (bottom) 1.5 c/w
9 TPS65216 www.ti.com slds187 ? october 2018 submit documentation feedback product folder links: TPS65216 specifications copyright ? 2018, texas instruments incorporated 3.5 electrical characteristics over operating free-air temperature range (unless otherwise noted) parameter test conditions min typ max unit input voltage and currents v in_bias input supply voltage range normal operation 3.6 5.5 v eeprom programming 4.5 5.5 deglitch time 5 ms i off off state current, total current into in_bias, in_dcdcx, in_ldo1, in_ls v in = 3.6 v; all rails disabled. t j = 0 c to 85 c 5 a i suspend suspend current, total current into in_bias, in_dcdcx, in_ldo1, in_ls v in = 3.6 v; dcdc3 enabled, low-power mode, no load. all other rails disabled. t j = 0 c to 105 c 220 a int_ldo v int_ldo output voltage 2.5 v dc accuracy i out < 10 ma ? 2% 2% i out output current range maximum allowable external load 0 10 ma i limit short circuit current limit output shorted to gnd 23 ma t hold hold-up time measured from v int_ldo = to v int_ldo = 1.8 v all rails enabled before power off, v in_bias = 2.8 v to 0 v in < no external load on int_ldo c int_ldo = , see table 5-3 150 ms c out nominal output capacitor value ceramic, x5r or x7r, see table 5-3 0.1 1 22 f tolerance ceramic, x5r or x7r, rated voltage 6.3 v ? 20% 20% dcdc1 (1.1-v buck) v in_dcdc1 input voltage range v in_bias > v uvlo 3.6 5.5 v v dcdc1 output voltage range adjustable through i 2 c 0.85 1.675 v dc accuracy 3.6 v v in 5.5 v; 0 a i out 1.8 a ? 2% 2% dynamic accuracy in respect to nominal output voltage i out = 50 ma to 450 ma in < 1 s c out 10 f, over full input voltage range ? 2.5% 2.5% i out continuous output current v in_dcdc1 > 3.6 v 1.8 a i q quiescent current total current from i n_dcdc1 pin; device not switching, no load 25 50 a r ds(on) high-side fet on resistance v in_dcdc1 = 3.6 v 230 355 m low-side fet on resistance v in_dcdc1 = 3.6 v 90 145 i limit high-side current limit v in_dcdc1 = 3.6 v 2.8 a low-side current limit v in_dcdc1 = 3.6 v 3.1 v pg power-good threshold v out falling strict = 0b 88.5% 90% 91.5% strict = 1b 96% 96.5% 97% hysteresis v out rising strict = 0b 3.8% 4.1% 4.4% strict = 1b 0.25% deglitch v out falling strict = 0b 1 ms strict = 1b 50 s v out rising strict = 0b 10 s strict = 1b 10 s time-out 5 ms v ov overvoltage detection threshold v out rising, strict = 1b 103% 103.5% 104% hysteresis v out falling, strict = 1b 0.25% deglitch v out rising, strict = 1b 50 s i inrush inrush current v in_dcdc1 = 3.6 v; c out = 10 f to 100 f 500 ma
10 TPS65216 slds187 ? october 2018 www.ti.com submit documentation feedback product folder links: TPS65216 specifications copyright ? 2018, texas instruments incorporated electrical characteristics (continued) over operating free-air temperature range (unless otherwise noted) parameter test conditions min typ max unit (1) 500- f of remote capacitance can be supported for dcdc1/2. r dis discharge resistor 150 250 350 l nominal inductor value see table 5-2 1 1.5 2.2 h tolerance ? 30% 30% c out output capacitance value ceramic, x5r or x7r, see table 5-3 10 22 100 (1) f dcdc2 (1.1-v buck) v in_dcdc2 input voltage range v in_bias > v uvlo 3.6 5.5 v v dcdc2 output voltage range adjustable through i 2 c 0.85 1.675 v dc accuracy 3.6 v v in 5.5 v; 0 a i out 1.8 a ? 2% 2% dynamic accuracy in respect to nominal output voltage i out = 50 ma to 450 ma in < 1 s c out 10 f, over full input voltage range ? 2.5% 2.5% i out continuous output current v in_dcdc2 > 3.6 v 1.8 a i q quiescent current total current from i n_dcdc2 pin; device not switching, no load 25 50 a r ds(on) high-side fet on resistance v in_dcdc2 = 3.6 v 230 355 m low-side fet on resistance v in_dcdc2 = 3.6 v 90 145 i limit high-side current limit v in_dcdc2 = 3.6 v 2.8 a low-side current limit v in_dcdc2 = 3.6 v 3.1 v pg power-good threshold v out falling strict = 0b 88.5% 90% 91.5% strict = 1b 96% 96.5% 97% hysteresis v out rising strict = 0b 3.8% 4.1% 4.4% strict = 1b 0.25% deglitch v out falling strict = 0b 1 ms strict = 1b 50 s v out rising strict = 0b 10 s strict = 1b 10 s time-out occurs at enable of dcdc2 and after dcdc2 register write (register 0x17) 5 ms v ov overvoltage detection threshold v out rising, strict = 1b 103% 103.5% 104% hysteresis v out falling, strict = 1b 0.25% deglitch v out rising, strict = 1b 50 s i inrush inrush current v in_dcdc2 = 3.6 v; c out = 10 f to 100 f 500 ma r dis discharge resistor 150 250 350 l nominal inductor value see table 5-2 1 1.5 2.2 h tolerance ? 30% 30% c out output capacitance value ceramic, x5r or x7r, see table 5-3 10 22 100 (1) f dcdc3 (1.2-v buck) v in_dcdc3 input voltage range v in_bias > v uvlo 3.6 5.5 v v dcdc3 output voltage range adjustable through i 2 c 0.9 3.4 v dc accuracy 3.6 v v in 5.5 v; 0 a i out 1.8 a, v in_dcdc3 (v dcdc3 + 700 mv) ? 2% 2% dynamic accuracy in respect to nominal output voltage i out = 50 ma to 450 ma in < 1 s c out 10 f, over full input voltage range ? 2.5% ? 2.5% i out continuous output current v in_dcdc3 > 3.6 v 1.8 a i q quiescent current total current from in_dcdc3 pin; device not switching, no load 25 50 a
11 TPS65216 www.ti.com slds187 ? october 2018 submit documentation feedback product folder links: TPS65216 specifications copyright ? 2018, texas instruments incorporated electrical characteristics (continued) over operating free-air temperature range (unless otherwise noted) parameter test conditions min typ max unit r ds(on) high-side fet on resistance v in_dcdc3 = 3.6 v 230 345 m low-side fet on resistance v in_dcdc3 = 3.6 v 100 150 i limit high-side current limit v in_dcdc3 = 3.6 v 2.8 a low-side current limit v in_dcdc3 = 3.6 v 3 v pg power-good threshold v out falling strict = 0b 88.5% 90% 91.5% strict = 1b 95% 95.5% 96% hysteresis v out rising strict = 0b 3.8% 4.1% 4.4% strict = 1b 0.25% deglitch v out falling strict = 0b 1 ms strict = 1b 50 s v out rising strict = 0b 10 s strict = 1b 10 s time-out occurs at enable of dcdc3 and after dcdc3 register write (register 0x18) 5 ms v ov overvoltage detection threshold v out rising, strict = 1b 104% 104.5% 105% hysteresis v out falling, strict = 1b 0.25% deglitch v out rising, strict = 1b 50 s i inrush inrush current v in_dcdc3 = 3.6 v; c out = 10 f to 100 f 500 ma r dis discharge resistor 150 250 350 l nominal inductor value see table 5-2 1.0 1.5 2.2 h tolerance ? 30% 30% c out output capacitance value ceramic, x5r or x7r, see table 5-3 10 22 100 f dcdc4 (3.3-v buck-boost) / analog and i/o v in_dcdc4 input voltage operating range v in_bias > v uvlo , ? 40 c to +105 c 3.6 5.5 v v dcdc4 output voltage range adjustable through i 2 c 1.175 3.3 v v dcdc4 dc accuracy 4.2 v v in 5.5 v; 3 v < v out 3.4 v 0 a i out 1.6 a ? 2% 2% 3.3 v v in 4.2 v; 3 v < v out 3.4 v 0 a i out 1.3 a ? 2% 2% 2.8 v v in 5.5 v; 1.65 v < v out 3 v 0 a i out 1 a ? 2% 2% 2.8 v v in 5.5 v; 1.175 v < v out 1.65 v 0 a i out 1 a ? 2.5% 2.5% output voltage ripple pfm mode enabled; 4.2 v v in 5.5 v; 0 a i out v out = 3.3 v mv pp minimum duty cycle in step- down mode 18% i out continuous output current v in_dcdc4 = 2.8 v, v out = 3.3 v 1 a v in_dcdc4 = 3.6 v, v out = 3.3 v 1.3 v in_dcdc4 = 5 v, v out = 3.3 v 1.6 i q quiescent current total current from in_dcdc4 pin; device not switching, no load 25 50 a f sw switching frequency 2400 khz
12 TPS65216 slds187 ? october 2018 www.ti.com submit documentation feedback product folder links: TPS65216 specifications copyright ? 2018, texas instruments incorporated electrical characteristics (continued) over operating free-air temperature range (unless otherwise noted) parameter test conditions min typ max unit r ds(on) high-side fet on resistance v in_dcdc3 = 3.6 v in_dcdc4 to l4a 166 m l4b to dcdc4 149 low-side fet on resistance v in_dcdc3 = 3.6 v l4a to gnd 142 190 l4b to gnd 144 190 i limit average switch current limit v in_dcdc4 = 3.6 v 3000 ma v pg power-good threshold v out falling strict = 0b 88.5% 90% 91.5% strict = 1b 95% 95.5% 96% hysteresis v out rising strict = 0b 3.8% 4.1% 4.4% strict = 1b 0.25% deglitch v out falling strict = 0b 1 ms strict = 1b 50 s v out rising strict = 0b 10 s strict = 1b 10 s time-out occurs at enable of dcdc4 and after dcdc4 register write (register 0x19) 5 ms v ov overvoltage detection threshold v out rising, strict = 1b 104% 104.5% 105% hysteresis v out falling, strict = 1b 0.25% deglitch v out rising, strict = 1b 50 s i inrush inrush current v in_dcdc4 = 3.6 v v indcdc4 5.5 v; 40 f c out 100 f 500 ma r dis discharge resistor 150 250 350 l nominal inductor value see table 5-2 1.2 1.5 2.2 h tolerance ? 30% 30% c out output capacitance value ceramic, x5r or x7r, see table 5-3 40 80 100 f
13 TPS65216 www.ti.com slds187 ? october 2018 submit documentation feedback product folder links: TPS65216 specifications copyright ? 2018, texas instruments incorporated electrical characteristics (continued) over operating free-air temperature range (unless otherwise noted) parameter test conditions min typ max unit (2) discharge function disabled by default. (3) switch is temporarily turned off if input voltage drops below uvlo threshold. ldo1 (1.8-v ldo) v in_ldo1 input voltage range v in_bias > v uvlo 1.8 5.5 v i q quiescent current no load 35 a v out output voltage range adjustable through i 2 c 0.9 3.4 v dc accuracy v out + 0.2 v v in 5.5 v; 0 a i out 200 ma ? 2% 2% i out output current range v in_ldo1 ? v do = v out 0 200 ma v in_ldo1 > 2.7 v, v out = 1.8 v 0 400 i limit short circuit current limit output shorted to gnd 445 550 ma v do dropout voltage i out = 100 ma, v in = 3.6 v 200 mv v pg power-good threshold v out falling strict = 0b 86% 90% 94% strict = 1b 95% 95.5% 96% hysteresis, v out rising strict = 0b 3% 4% 5% strict = 1b 0.25% deglitch v out falling strict = 0b 1 ms strict = 1b 50 s v out rising strict = 0b 10 s strict = 1b 10 s time-out 5 ms v ov overvoltage detection threshold v out rising, strict = 1b 104% 104.5% 105% hysteresis v out falling, strict = 1b 0.25% deglitch v out rising, strict = 1b 50 s v out falling, strict = 1b 1 ms r dis discharge resistor 150 250 380 c out output capacitance value ceramic, x5r or x7r 22 100 f load switch v in_ls input voltage range v in_bias > v uvlo 1.8 10 v r ds(on) static on resistance v in_ls = 9 v, i out = 500 ma, over full temperature range 440 m v in_ls = 5 v, i out = 500 ma, over full temperature range 526 v in_ls = 2.8 v, i out = 200 ma, over full temperature range 656 v in_ls = 1.8 v, i out = 200 ma, over full temperature range 910 i limit short circuit current limit v in_ls > 2.3 v, output shorted to gnd lsilim[1:0] = 00b 98 126 ma lsilim[1:0] = 01b 194 253 lsilim[1:0] = 10b 475 738 lsilim[1:0] = 11b 900 1234 v in_ls 2.3 v, output shorted to gnd lsilim[1:0] = 00b 98 126 lsilim[1:0] = 01b 194 253 lsilim[1:0] = 10b 475 738 t blank interrupt blanking time output shorted to gnd until interrupt is triggered 15 ms r dis internal discharge resistor at output (2) lsdchrg = 1 650 1000 1500 t ots overtemperature shutdown (3) 125 132 139 c hysteresis 10 c
14 TPS65216 slds187 ? october 2018 www.ti.com submit documentation feedback product folder links: TPS65216 specifications copyright ? 2018, texas instruments incorporated electrical characteristics (continued) over operating free-air temperature range (unless otherwise noted) parameter test conditions min typ max unit c out nominal output capacitance value ceramic, x5r or x7r, see table 5-3 1 100 220 f i/o levels and timing characteristics pg dly pgood delay time pgdly[1:0] = 00b 10 ms pgdly[1:0] = 01b 20 pgdly[1:0] = 10b 50 pgdly[1:0] = 11b 150 t dg deglitch time pb input rising edge 100 ms falling edge 50 ms ac_det input rising edge 100 s falling edge 10 ms pwr_en input rising edge 10 ms falling edge 100 s gpio1 rising edge 1 ms falling edge 1 ms gpio2 rising edge 5 s falling edge 5 s t reset reset time pb input held low trst = 0b 8 s trst = 1b 15 v ih high level input voltage scl, sda, gpio1, gpio2 1.3 v ac_det, pb 0.66 in_bias pwr_en 1.3 v il low level input voltage scl, sda, pwr_en, ac_det, pb, gpio1, gpio2 0 0.4 v v ol low level output voltage nwakeup, nint, sda, pgood, gpio1, gpio2; i sink = 2 ma 0 0.3 v npfo; i sink = 2 ma 0 0.35 v pfi power-fail comparator threshold input falling 800 mv hysteresis input rising 40 mv accuracy ? 4% 4% deglitch input falling 25 s input rising 10 ms i dc34_sel dc34_sel bias current enabled only at power-up 10 a v dc34_sel dcdc3 / dcdc4 power-up default selection thresholds threshold 1 100 mv threshold 2 163 threshold 3 275 threshold 4 400 threshold 5 575 threshold 6 825 threshold 7 1200
15 TPS65216 www.ti.com slds187 ? october 2018 submit documentation feedback product folder links: TPS65216 specifications copyright ? 2018, texas instruments incorporated electrical characteristics (continued) over operating free-air temperature range (unless otherwise noted) parameter test conditions min typ max unit (4) configured as input. (5) configured as output. r dc34_sel dcdc3 / dcdc4 power-up default selection resistor values setting 0 0 0 7.7 k setting 1 12.1 setting 2 20 setting 3 30.9 31.6 32.3 setting 4 45.3 setting 5 setting 6 95.3 setting 7 150 i bias input bias current scl, sda, gpio1 (4) , gpio2 (4) ; v in = 3.3 v 0.01 1 a pb, ac_det, pfi; v in = 3.3 v 500 na i leak pin leakage current nint, nwakeup, npfo, pgood, pwr_en, gpio1 (5) , gpio2 (5) v out = 3.3 v 500 na oscillator ? osc oscillator frequency 2400 khz frequency accuracy t j = ? 40 c to +105 c ? 12% 12% t ots overtemperature shutdown increasing junction temperature 135 145 155 c hysteresis decreasing junction temperature 20 t warn high-temperature warning increasing junction temperature 90 100 110 c hysteresis decreasing junction temperature 15 (1) the scl duty cycle at 400 khz must be > 40%. 3.6 timing requirements min nom max unit f scl serial clock frequency 100 khz 400 t hd;sta hold time (repeated) start condition. after this period, the first clock pulse is generated. scl = 100 khz 4 s scl = 400 khz 600 ns t low low period of the scl clock scl = 100 khz 4.7 s scl = 400 khz 1.3 t high high period of the scl clock scl = 100 khz 4 s scl = 400 khz (1) 1 t su;sta set-up time for a repeated start condition scl = 100 khz 4.7 s scl = 400 khz 600 ns t hd;dat data hold time scl = 100 khz 0 3.45 s scl = 400 khz 0 900 ns t su;dat data set-up time scl = 100 khz 250 ns scl = 400 khz 100 t r rise time of both sda and scl signals scl = 100 khz 1000 ns scl = 400 khz 300 t f fall time of both sda and scl signals scl = 100 khz 300 ns scl = 400 khz 300 t su;sto set-up time for stop condition scl = 100 khz 4 s scl = 400 khz 600 ns
16 TPS65216 slds187 ? october 2018 www.ti.com submit documentation feedback product folder links: TPS65216 specifications copyright ? 2018, texas instruments incorporated timing requirements (continued) min nom max unit (2) the inputs of i 2 c devices in standard-mode do not require spike suppression. t buf bus free time between stop and start condition scl = 100 khz 4.7 s scl = 400 khz 1.3 t sp pulse width of spikes which must be suppressed by the input filter scl = 100 khz ? (2) ? (2) ns scl = 400 khz 0 50 c b capacitive load for each bus line scl = 100 khz 400 pf scl = 400 khz 400
17 TPS65216 www.ti.com slds187 ? october 2018 submit documentation feedback product folder links: TPS65216 specifications copyright ? 2018, texas instruments incorporated 3.7 typical characteristics at t j = 25 c unless otherwise noted v out = 1.1 v figure 3-1. dcdc1 accuracy v out = 1.1 v figure 3-2. dcdc2 accuracy v out = 1.2 v figure 3-3. dcdc3 accuracy v out = 3.3 v figure 3-4. dcdc4 accuracy output current (a) accuracy 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 -0.55% -0.5% -0.45% -0.4% -0.35% -0.3% -0.25% -0.2% -0.15% -0.1% -0.05% 0 0.05% 0.1% 0.15% d002 v = 3.6 v in v in = 5 v output current (a) accuracy 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 -0.25% -0.2% -0.15% -0.1% -0.05% 0 0.05% 0.1% d003 v = 3.6 v in v in = 5 v output current (a) accuracy 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 -0.4% -0.35% -0.3% -0.25% -0.2% -0.15% -0.1% -0.05% 0 0.05% 0.1% 0.15% 0.2% 0.25% 0.3% d001 v = 3.6 v in v in = 5 v output current (a) accuracy 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 -1.25% -1% -0.75% -0.5% -0.25% 0 0.25% 0.5% 0.75% d004 v = 3.6 v in v in = 5 v
18 TPS65216 slds187 ? october 2018 www.ti.com submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated 4 detailed description 4.1 overview the TPS65216 provides three step-down converters three general-purpose i/os , one buck-boost converter, one load switch and one ldo. the system can be supplied by a regulated 5-v supply. the device is characterized across a ? 40 c to +105 c temperature range, which makes it suitable for various industrial applications. the i 2 c interface provides comprehensive features for using TPS65216. all rails, the load switch, and gpios can be enabled / disabled. voltage thresholds for the uvlo and supervisor can be customized. power-up and power-down sequences can also be programmed through i 2 c. interrupts for overtemperature, overcurrent, and undervoltage can be monitored for the load-switch. the integrated voltage supervisor monitors dcdc 1-4 and ldo1. it has two settings; the standard settings only monitor for undervoltage, while the strict settings implement tight tolerances on both undervoltage and overvoltage. a power good signal is provided to report the regulation state of the five rails. the three hysteretic step-down converters can each supply up to 1.8 a of current. the default output voltages for each converter can be adjusted through the i 2 c interface. dcdc 1 and 2 feature dynamic voltage scaling with adjustable slew rate. the step-down converters operate in a low power mode at light load, and can be forced into pwm operation for noise sensitive applications.
19 TPS65216 www.ti.com slds187 ? october 2018 submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated 4.2 functional block diagram thermal pad dc34_sel pfi scl sda pwr_en ac_det pb npfo pgood nwakeup nint gpio1 gpio2 l1 fb1 dcdc1 10 ? f 10 h 1.1-v core supply (adjustable) in_dcdc1 4.7 ? f from 3.6-v to 5.5-v system power l2 fb2 dcdc2 10 ? f 10 h 1.1-v mpu supply (adjustable) in_dcdc2 4.7 ? f from 3.6-v to 5.5-v system power l3 fb3 dcdc3 10 ? f 1.5-v ddr3 supply (adjustable) in_dcdc3 4.7 ? f from 3.6-v to 5.5-v system power l4a l4b dcdc4 3.3-v i/o supply (adjustable) in_dcdc4 4.7 ? f from 3.6-v to 5.5-v system power dcdc4 100 nf ls ls 500-ma load switch in_ls from 1.8-v to 10-v supply 10 ? f ldo1 ldo1 0.9-v to 3.3-v analog supply (adjustable, default 1.8 v) in_ldo1 from 1.8-v to 5.5-v supply 10 ? f int_ldo bias in_bias from 3.6-v to 5.5-v system power 1 ? f vselect supervisor and up, down sequencer ldo1 vdcdc4 vdcdc3 vdcdc2 vdcdc1 digital i 2 c + v ref from soc from soc 10 vio 10 vio 100 k in_bias 100 k 100 k in_bias from soc from external charger momentary push-button to soc to soc to soc to soc to/from soc to soc od od od od od od vio (1.8 v / 3.3 v) copyright ? 2018, texas instruments incorporated input power 47 ? f
20 TPS65216 slds187 ? october 2018 www.ti.com submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated 4.3 feature description 4.3.1 wake-up and power-up and power-down sequencing the TPS65216 has a predefined power-up and power-down sequence, which in a typical application does not need to be changed. the user can define custom sequences with i 2 c. the power-up sequence is defined by a series of ten strobes and nine delay times. each output rail is assigned to a strobe to determine the order of enabling rails. a single rail is assigned to only one strobe, but multiple rails can be assigned to the same strobe. the delay times between strobes are between 2 ms and 5 ms. 4.3.1.1 power-up sequencing when the power-up sequence initiates, strobe1 occurs, and any rail assigned to this strobe is enabled. after a delay time of dly1, strobe2 occurs and the rail assigned to this strobe is powered up. the sequence continues until all strobes occur and all dlyx times execute. strobe assignments and delay times are defined in the seqx registers, and are changed under i 2 c control. the power-up sequence executes if one of the following events occurs: ? from the off state: ? the push-button (pb) is pressed (falling edge on pb) or ? the ac_det pin is pulled low (falling edge) or ? the pwr_en is asserted (driven to high-level) or ? the main power is connected (in_bias) and ac_det is grounded and ? the device is not in undervoltage lockout (uvlo) or overtemperature shutdown (ots). ? from the pre_off state: ? the pb is pressed (falling edge on pb) or ? the ac_det pin is pulled low (falling edge) or ? pwr_en is asserted (driven to high-level) and ? the device is not in uvlo or ots. ? from the suspend state: ? the pb is pressed (falling edge on pb) or ? the ac_det pin is pulled low (falling edge) or ? the pwr_en pin is pulled high (level sensitive) and ? the device is not in uvlo or ots. when a power-up event is detected, the device enters a wait_pwr_en state and triggers the power-up sequence. the device remains in wait_pwr_en as long as the pwr_en and either the pb or ac_det pin are held low. if both, the pb and ac_det return to logic-high state and the pwr_en pin has not been asserted within 20 s of entering wait_pwr_en state, the power-down sequence is triggered and the device returns to off state. once pwr_en is asserted, the device advances to active state, which is functionally equivalent to wait_pwr_en. however, the ac_det pin is ignored and power-down is controlled by the pwr_en pin only. rails not assigned to a strobe (seq = 0000b) are not affected by power-up and power-down sequencing and remain in their current on/off state regardless of the sequencer. a rail can be enabled/disabled at any time by setting the corresponding enable bit in the enablex register, with the exception that the enablex register cannot be accessed while the sequencer is active. enable bits always reflect the current enable state of the rail, for example the sequencer sets and resets the enable bits for the rails under its control. note the power-up sequence is defined by strobes and delay times, and can be triggered by the pb, ac_det (not shown, same as pb), or pwr_en pin.
21 TPS65216 www.ti.com slds187 ? october 2018 submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated push-button deglitch time is not shown. figure 4-1. power-up sequences from off or suspend state; pb is power-up event figure 4-2. power-up sequences from suspend state; pwr_en is power-up event figure 4-3. power-up sequences from recovery state pwr_en (input) nwakeup (output) pb (input) dly3 dly4 strobe 3 seq = 0011b strobe 4 seq = 0100b strobe 5 seq = 0101b strobe1 seq = 0001b strobe2 seq = 0010b dly1 dly5 strobe 6 seq = 0110b dly6 strobe 7 seq = 0111b strobe 8 seq = 1000b strobe 9 seq = 1001b strobe 10 seq = 1010b dly7 dly8 dly9 dly2 pwr_en (input) nwakeup (output) pb (input) dly3 dly4 strobe 3 seq = 0011b strobe 4 seq = 0100b strobe 5 seq = 0101b strobe1 seq = 0001b strobe2 seq = 0010b dly1 dly5 strobe 6 seq = 0110b dly6 strobe 7 seq = 0111b strobe 8 seq = 1000b strobe 9 seq = 1001b strobe 10 seq = 1010b dly7 dly8 dly9 dly2 fault recovery pwr_en (input) nwakeup (output) pb (input) dly3 dly4 strobe 3 seq = 0011b strobe 4 seq = 0100b strobe 5 seq = 0101b strobe1 seq = 0001b strobe2 seq = 0010b dly1 dly5 strobe 6 seq = 0110b dly6 strobe 7 seq = 0111b strobe 8 seq = 1000b strobe 9 seq = 1001b strobe 10 seq = 1010b dly7 dly8 dly9 dly2
22 TPS65216 slds187 ? october 2018 www.ti.com submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated 4.3.1.2 power-down sequencing by default, the power-down sequence follows the reverse of the power-up sequence. when the power- down sequence is triggered, strobe10 occurs and any rail assigned to strobe10 is shut down and its discharge circuit is enabled. after a delay time of dly9, strobe9 occurs and any rail assigned to it is shut down and its discharge circuit is enabled. the sequence continues until all strobes occur and all dlyx times execute. the dlyx times are extended by a factor of 10x to provide ample time for discharge, and preventing output voltages from crossing during shut-down. the dlyfctr bit is applied globally to all power-down delay times. regardless of the dlyx and dlyfctr settings, the pmic enters off, suspend, or recovery state 500 ms after the power-down sequence initiates, to ensure that the discharge circuits remain enabled for a minimum of 150 ms before the next power-up sequence starts. a power-down sequence executes if one of the following events occurs: ? the device is in the wait_pwr_en state, the pb and ac_det pins are high, pwr_en is low, and the 20-s timer has expired. ? the device is in the active state and the pwr_en pin is pulled low. ? the device is in the wait_pwr_en, active, or suspend state and the push-button is held low for > 8 s (15 s if trst = 1b) ? a fault occurs in the ic (ots, uvlo, pgood failure). when transitioning from active to suspend state, rails not controlled by the power-down sequencer maintains the same on/off state in suspend state that it had in active state. this allows for the selected power rails to remain powered up when in the suspend state. when transitioning to the off or recovery state, rails not under sequencer control are shut-down as follows: ? dcdc1, 2, 3, 4, , and ldo1 shut down at the beginning of the power-down sequence, if not under sequencer control (seq = 0b). ? ls shuts down as the state machine enters an off or recovery state; 500 ms after the power- down sequence is triggered. if the supply voltage on in_bias drops below 2.5 v, the digital core is reset and all power rails are shut down instantaneously and are pulled low to ground by their internal discharge circuitry (dcdc1-4, and ldo1). the amount of time the discharge circuitry remains active is a function of the int_ldo hold up time (see section 4.3.1.5 for more details). 4.3.1.3 strobes 1 and 2 strobe1 and strobe2 are special strobes that are not used in the TPS65216 device, but strobe1 and strobe2 are still executed for power-up. the power-up sequence starts at strobe3 after dly1 and dly2 timers. the power-down sequence ends at strobe3.
23 TPS65216 www.ti.com slds187 ? october 2018 submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated figure 4-4. power-down sequences to off state; pwr_en is power-down event strobe2 and strobe1 are not shown. figure 4-5. power-down sequences to suspend state; pwr_en is power-down event strobe2 and strobe1 are not shown. figure 4-6. power-down sequences to recovery state; tsd or uv is power-down event pwr_en (input) nwakeup (output) pb (input) dly3 dly4 strobe 3 seq = 0011b strobe 4 seq = 0100b strobe 5 seq = 0101b dly5 strobe 6 seq = 0110b dly6 strobe 7 seq = 0111b strobe 8 seq = 1000b strobe 9 seq = 1001b strobe 10 seq = 1010b dly7 dly8 dly9 fault pwr_en (input) nwakeup (output) pb (input) dly3 dly4 strobe 3 seq = 0011b strobe 4 seq = 0100b strobe 5 seq = 0101b strobe1 seq = 0001b strobe2 seq = 0010b dly1 dly5 strobe 6 seq = 0110b dly6 strobe 7 seq = 0111b strobe 8 seq = 1000b strobe 9 seq = 1001b strobe 10 seq = 1010b dly7 dly8 dly9 dly2 pwr_en (input) nwakeup (output) pb (input) dly3 dly4 strobe 3 seq = 0011b strobe 4 seq = 0100b strobe 5 seq = 0101b dly5 strobe 6 seq = 0110b dly6 strobe 7 seq = 0111b strobe 8 seq = 1000b strobe 9 seq = 1001b strobe 10 seq = 1010b dly7 dly8 dly9
24 TPS65216 slds187 ? october 2018 www.ti.com submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated 4.3.1.4 supply voltage supervisor and power good (pgood) power-good (pgood) is an open-drain output of the built-in voltage supervisor that monitors dcdc1, dcdc2, dcdc3, dcdc4, and ldo1. the output is hi-z when all enabled rails are in regulation and driven low when one or more rails encounter a fault which brings the output voltage outside the specified tolerance range. in a typical application pgood drives the reset signal of the soc. the supervisor has two modes of operation, controlled by the strict bit. with the strict bit set to 0, all enabled rails of the five regulators are monitored for undervoltage only with relaxed thresholds and deglitch times. with the strct bit set to 1, all enabled rails of the five regulators are monitored for undervoltage and overvoltage with tight limits and short deglitch times. table 4-1 summarizes these details. table 4-1. supervisor characteristics controlled by the strict bit parameter strict = 0b (typ) strict = 1b (typ) undervoltage monitoring threshold (output falling) 90% 96.5% (dcdc1, dcdc2) 95.5% (dcdc3, dcdc4, ldo1) deglitch (output falling) 1 ms 50 s deglitch (output rising) 10 s 10 s overvoltage monitoring threshold (output falling) n/a 103.5% (dcdc1, dcdc2) 104.5% (dcdc3, dcdc4, ldo1) deglitch (output falling) n/a 1 ms deglitch (output rising) n/a 50 s figure 4-7. definition of undervoltage, overvoltage thresholds, hysteresis, and deglitch times the following rules apply to the pgood output: ? the power-up default state for pgood is low. when all rails are disabled, pgood output is driven low. ? only enabled rails are monitored. disabled rails are ignored. ? power-good monitoring of a particular rail starts 5 ms after the rail is enabled and is continuously monitored thereafter. this allows the rail to power-up. ? pgood is delayed by pgdly time after the sequencer is finished and the last rail is enabled. ? if an enabled rail is continuously outside the monitoring threshold for longer than the deglitch time, pgood is pulled low, and all rails are shut-down following the power-down sequence. pgdly does not apply. ldo1 power-good comparator output (internal signal) undervoltage threshold (output falling) hysteresis pgood voltage droop has no effect on pgood output if duration is less than deglitch time. overvoltage threshold (output rising) voltage droop has no effect on pgood output if duration is less than deglitch time. hysteresis deglitch time
25 TPS65216 www.ti.com slds187 ? october 2018 submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated ? disabling a rail manually by resetting the dcx_en or ldo1_en bit has no effect on the pgood pin. if all rails are disabled, pgood is driven low as the last rail is disabled. ? if the power-down sequencer is triggered, pgood is driven low. ? pgood is driven low in suspend state, regardless of the number of rails that are enabled. figure 4-8 shows a typical power-up sequence and pgood timing. figure 4-8. typical power-up sequence of the main output rails 4.3.1.5 internal ldo (int_ldo) the internal ldo provides a regulated voltage to the internal digital core and analog circuitry. the internal ldo has a nominal output voltage of 2.5 v and can support up to 10 ma of external load. when system power fails, the uvlo comparator triggers the power-down sequence. if system power drops below , the digital core is reset and all remaining power rails are shut down instantaneously and are pulled low to ground by their internal discharge circuitry (dcdc1-4, and ldo1). the internal ldo reverse blocks to prevent the discharging of the output capacitor (c int_ldo ) on the int_ldo pin. the remaining charge on the int_ldo output capacitor provides a supply for the power rail discharge circuitry to ensure the outputs are discharged to ground even if the system supply has failed. the amount of hold-up time specified in section 3.5 is a function of the output capacitor value (c int_ldo ) and the amount of external load on the int_ldo pin, if any. the design allows for enough hold-up time to sufficiently discharge dcdc1-4, and ldo1 to ensure proper processor power-down sequencing. dcdc2 pwr_en (deglitched) pg dcdc3 (internal) dcdc1 dcdc4 pg dcdc4 (internal) vsys dcdc3 pg dcdc2 (internal) pg dcdc1 (internal) ldo1 pg ldo1 (internal) 5 ms pgood pg_dly 5 ms 5 ms 5 ms dly3 + dly4 dly5 + dly6 dly9 dly7 dly6 + dly5 fault dly8 dly8 nwakeup pb 5 s (maximum) dly7 dly4 + dly3 dly1 + dly2 5 ms
26 TPS65216 slds187 ? october 2018 www.ti.com submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated figure 4-9. internal ldo and uvlo sensing 4.3.1.6 current limited load switch the TPS65216 provides a current limited load switch with individual enable control. the load switch provides the following control and diagnostic features: ? the on/off state of the switch is controlled by the corresponding ls_en bit in the enable register. ? the load switch can only be controlled through i 2 c communication. the sequencer has no control over the load switch. ? the load switch has an active discharge function, disabled by default, and enabled through the lsdchrg bit. when enabled, the switch output is discharged to ground whenever the switch is disabled. ? when the pfi input drops below the power-fail threshold (the power-fail comparator trips), the load switch is automatically disabled to shed system load. this function must be individually through the corresponding lsnpfo bit. the switch does not turn back on automatically as the system voltage recovers, and must be manually re-enabled. ? an interrupt (ls_i) issues whenever the load switch actively limits the output current, such as when the output load exceeds the current limit value. the switch remains on and provides current to the load according to the current-limit setting. ? the load switch has a local overtemperature sensor which disables the switch if the power dissipation and junction temperature exceeds safe operating value. the switch automatically recovers once the temperature drops below the ots threshold value minus hysteresis. the ls_f (fault) interrupt bit is set while the switch is held off by the ots function. the load switch (ls) is a non-reverse blocking, medium-voltage ( < 10 v), low-impedance switch that can be used to provide 1.8-v to 10-v power to an auxiliary port. ls has four selectable current limit values that are selectable through lsilim[1:0]. in_bias int_ldo digital core power-rail discharge circuitry eeprom from system power 10 ? f uvlo reset
27 TPS65216 www.ti.com slds187 ? october 2018 submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated figure 4-10. typical application of load switch 4.3.1.7 ldo1 ldo1 is a general-purpose ldo intended to provide power to analog circuitry on the soc. ldo1 has an input voltage range from 1.8 v to 5.5 v, and can be connected either directly to the system power or the output of a dcdc converter. the output voltage is programmable in the range of 0.9 v to 3.4 v with a default of 1.8 v. ldo1 supports up to 200 ma at the minimum specified headroom voltage, and up to 400 ma at the typical operating condition of v out = 1.8 v, v in_ldo1 > 2.7 v. 4.3.1.8 uvlo depending on the slew rate of the input voltage into the in_bias pin, the power rails of TPS65216will be enabled at either v ulvo or v ulvo + v hys . if the slew rate of the in_bias voltage is greater than 30 v/s, then TPS65216 will power up at v ulvo . once the input voltage rises above this level, the input voltage may drop to the v uvlo level before the pmic shuts down. in this scenario, if the input voltage were to fall below v uvlo but above 2.55 v, the input voltage would have to recover above v uvlo in less than 5 ms for the device to remain active. if the slew rate of the in_bias voltage is less than 30 v/s, then TPS65216 will power up at v ulvo + v hys . once the input voltage rises above this level, the input voltage may drop to the v uvlo level before the pmic shuts down. in this scenario, if the input voltage were to fall below v uvlo but above 2.5 v, the input voltage would have to recover above v uvlo + v hys in less than 5 ms for the device to remain active. in either slew rate scenario, if the input voltage were to fall below 2.5 v, the digital core is reset and all remaining power rails are shut down instantaneously and are pulled low to ground by their internal discharge circuitry (dcdc1-4, and ldo1). from any 1.8-v to 10-v supply ls_i ls_en lsnpfo lsdis ls_f lsilim[1:0] in_ls ls 250 aux port vport gnd 0.1 ? f 120 ? f
28 TPS65216 slds187 ? october 2018 www.ti.com submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated figure 4-11. definition of uvlo and hysteresis after the uvlo triggers, the internal ldo blocks current flow from its output capacitor back to the in_bias pin, allowing the digital core and the discharge circuits to remain powered for a limited amount of time to properly shut-down and discharge the output rails. the hold-up time is determined by the value of the capacitor connected to int_ldo. see section 4.3.1.5 for more details. v in_bias uvlo (internal signal) uvlo active uvlo inactive uvlo threshold, supply falling < 5 ms > 5-ms deglitch uvlo hysteresis
29 TPS65216 www.ti.com slds187 ? october 2018 submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated 4.3.1.9 power-fail comparator the power-fail comparator notifies the system host if the system supply voltage drops and the system is at risk of shutting down. the comparator has an internal 800-mv threshold and the trip-point is adjusted by an external resistor divider. by default, the power-fail comparator has no impact on any of the power rails or the load switch. the load switch can be configured to be disabled when the pfi comparator trips to shed system load and extend hold-up time. the power-fail comparator also triggers the power-down sequencer, such that all or selective rails power down when the system voltage fails. to tie the power-fail comparator into the power-down sequence, the offnpfo bit in the control register must be set to 1. the power-fail comparator cannot be monitored by software, such that no interrupt or status bit is associated to this function. figure 4-12. power-fail comparator simplified circuit and timing diagram v pfi npfo (pin) npfo inactive npfo active pfi threshold, supply falling <25 s 10-ms deglitch 25-s deglitch pfi hysteresis pfi v ref (800 mv) deglitch npfo system supply voltage +
30 TPS65216 slds187 ? october 2018 www.ti.com submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated 4.3.1.10 dcdc3 / dcdc4 power-up default selection figure 4-13. left: flow chart for selecting dcdc power-up default voltage right: comparator circuit table 4-2. power-up default values of dcdc3 and dcdc4 rsel [k ] power-up default min typ max dcdc3[5:0] dcdc4[5:0] 0 0 7.7 programmed default (1.2 v) programmed default (3.3 v) 12.1 0x12 (1.35 v) programmed default (3.3 v) 20 0x18 (1.5 v) programmed default (3.3 v) 30.9 31.6 32.3 0x1f (1.8 v) programmed default (3.3 v) 45.3 0x3d (3.3 v) 0x01 (1.2 v) programmed default (1.2 v) 0x07 (1.35 v) 95.3 programmed default (1.2 v) 0x0d (1.5 v) 150 tied to int_ldo programmed default (1.2 v) 0x14 (1.8 v) enable 10 a dc34_sel current source. enable comparators. wait 100 s latch comparator outputs; depending on result, over-write dcdc3[5:0] and / or dcdc4[5:0] power-up default. dc34_sel dcdc3[5:0] logic core dc34_sel current source disabled. all comparators disabled. sequence is triggered by any event forcing register reset 1200 mv 825 mv 575 mv disable comparators disable dc34_sel current source. start power-up sequencer source enable 10 a int_ldo 400 mv 275 mv 163 mv 100 mv dcdc4[5:0] v0 v1 v2 v3 v4 v5 v6 rsel + + + + + + +
31 TPS65216 www.ti.com slds187 ? october 2018 submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated 4.3.1.11 i/o configuration the device has two gpio pins which are configured as follows: ? gpio1: ? general-purpose, open-drain output controlled by gpo1 user bit or sequencer ? gpio2: ? general-purpose, open-drain output controlled by gpo2 user bit or sequencer ? reset input-signal for dcdc1 and dcdc2 table 4-3. gpio1 configuration gpo1 (user bit) gpio1 (i/o pin) comments 0 0 open-drain output, driving low 1 hiz open-drain output, hiz table 4-4. gpio2 configuration dc12_rst (eeprom) gpo2 (user bit) gpio2 (i/o pin) comments 0 0 0 open-drain output, driving low 0 1 hiz open-drain output, hiz 1 x active low gpio2 is dcdc1 and dcdc2 reset input signal to pmic (active low). see section 4.3.1.11.1 for details. 4.3.1.11.1 using gpio2 as reset signal to dcdc1 and dcdc2 with the dc12_rst bit set to 1, gpio2 is an edge-sensitive reset input to the pmic. the reset signal affects dcdc1 and dcdc2 only, so that only those two registers are reset to the power-up default whenever gpio2 input transitions from high to low, while all other registers maintain their current values. dcdc1 and dcdc2 transition back to the default value following the slew settings, and are not power cycled. this function recovers the processor from reset events while in low-power mode. figure 4-14. i/o pin logic gpio1 gpo1 (user register bit / sequencer control enabled) dcdc1/2 reset gpo3 (user register bit, sequencer control enabled) dc12_rst (eeprom: 0b = disabled, 1b = enabled) gpio2
32 TPS65216 slds187 ? october 2018 www.ti.com submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated 4.3.1.12 push button input (pb) the pb pin is a cmos-type input used to power-up the pmic. typically, the pb pin is connected to a momentary switch to ground and an external pullup resistor. the power-up sequence is triggered if the pb input is held low for 600 ms. figure 4-15. left: typical pb input circuit right: push-button input (pb) deglitch and power-up timing in active mode, the TPS65216 monitors the pb input and issues an interrupt when the pin status changes, such as when it drops below or rises above the pb input-low or input-high thresholds. the interrupt is masked by the pbm bit in the int_mask1 register. pb push button system power (5.5 v) 100 k <100 ms pb pin (input) 50 ms 100 ms pb deglitched (internal signal) power-up event (internal signal) 550 ms
33 TPS65216 www.ti.com slds187 ? october 2018 submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated figure 4-16. pb input-low or input-high thresholds note interrupts are issued whenever the pb pin status changes. the pb_state bit reflects the current status of the pb input. nwakeup is pulled low for 150 s on every falling edge of pb. int pin (output) pb_state bit i 2 c access to int register nwakeup int register is read through i 2 c while pb remains pressed. int pin is released, pb_state bit remains set. int register is read through i 2 c. int pin is released. int register is read through i 2 c. pb interrupt bit pb pin (50-ms deglitched input) pb is pressed, int pin is pulled low, pb_state bit is set pb is released. int pin is pulled low, pb_state bit is reset. pb is pressed, int pin is pulled low, pb_state bit is set pb is released before int register is read through i 2 c. int pin remains low, pb_state bit is reset 150 s
34 TPS65216 slds187 ? october 2018 www.ti.com submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated 4.3.1.12.1 signaling pb-low event on the nwakeup pin in active state, the nwakeup pin is pulled low for five 32-khz clock cycles (approximately 150 s) whenever a falling edge on the pb input is detected. this allows the host processor to wakeup from deep sleep mode of operation. it is recommended to pull-up the nwakeup pin to a i/o power supply through a pull-up resistor. for nwakeup to function properly in the suspend state, this pin must be pulled up to a power supply that is disconnected from the sequencer before entering suspend. . 4.3.1.12.2 push button reset if the pb input is pulled low for 8 s (15 s if trst = 1b) or longer, all rails are disabled, and the device enters the recovery state. the device powers up automatically after the 500 ms power-down sequence is complete, regardless of the state of the pb input. holding the pb pin low for 8 s (15 s if trst = 1b), only turns off the device temporarily and forces a system restart, and is not a power-down function. if the pb is held low continuously, the device power-cycles in 8-s and 15-s intervals. 4.3.1.13 ac_det input (ac_det) the ac_det pin is a cmos-type input used in three different ways to control the power-up of the pmic: ? in a battery operated system, ac_det is typically connected to an external battery charger with an open-drain power-good output pulled low when a valid charger supply is connected to the system. a falling edge on the ac_det pin causes the pmic to power up. ? in a non-portable system, the ac_det pin may be shorted to ground and the ic powers up whenever system power is applied to the chip. ? if none of the above behaviors are desired, ac_det may be tied to system power (in_bias). power- up is then controlled through the push-button input or pwr_en input. a. portable systems b. non-portable systems c. disabled figure 4-17. ac_det pin configurations figure 4-18. ac_det input deglitch and power-up timing (portable systems) <100 ms ac_det pin (input) 10 ms 100 ms ac_det deglitched (internal signal) power-up event (internal signal) (c) ac_det system power (5.5 v) (b) ac_det (a) ac_det system power (5.5 v) 100 k
35 TPS65216 www.ti.com slds187 ? october 2018 submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated in active state, the TPS65216 monitors the ac_det input and issues an interrupt when the pin status changes, such as when it drops below or rises above the ac_det input-low or input-high thresholds. the interrupt is masked by the acm bit in the int_mask1 register. figure 4-19. ac_state pin note interrupts are issued whenever the ac_det pin status changes. the ac_state bit reflects the current status of the ac_det input. 4.3.1.14 interrupt pin (int) the interrupt pin signals any event or fault condition to the host processor. whenever a fault or event occurs in the ic, the corresponding interrupt bit is set in the int register, and the open-drain output is pulled low. the int pin is released (returns to hi-z state) and fault bits are cleared when the host reads the int register. if a failure persists, the corresponding int bit remains set and the int pin is pulled low again after a maximum of 32 s. the mask register masks events from generating interrupts. the mask settings affect the int pin only, and have no impact on the protection and monitor circuits. int pin (output) ac_state bit i 2 c access to int register ac_det pin (10-ms deglitched input) ac goes low, int pin is pulled low, pc_state bit is set int register is read through i 2 c while ac remains low. int pin is released, ac_state bit remains set. ac goes high. int pin is pulled low, ac_state bit is reset. int register is read through i 2 c. int pin is released. ac goes low, int pin is pulled low, ac_state bit is set ac goes high before int register is read through i 2 c. int pin remains low, ac_state bit is reset int register is read through i 2 c. ac interrupt bit
36 TPS65216 slds187 ? october 2018 www.ti.com submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated (1) note: the scl duty cycle at 400 khz must be > 40%. 4.3.1.15 i 2 c bus operation the TPS65216 hosts a slave i 2 c interface (address 0x24) that supports data rates up to 400kbps, auto- increment addressing. (1) figure 4-20. subaddress in i 2 c transmission the i 2 c bus is a communications link between a controller and a series of slave terminals. the link is established using a two-wired bus consisting of a serial clock signal (scl) and a serial data signal (sda). the serial clock is sourced from the controller in all cases where the serial data line is bi-directional for data communication between the controller and the slave terminals. each device has an open drain output to transmit data on the serial data line. an external pullup resistor must be placed on the serial data line to pull the drain output high during data transmission. data transmission initiates with a start bit from the controller as shown in figure 4-22 . the start condition is recognized when the sda line transitions from high to low during the high portion of the scl signal. upon reception of a start bit, the device receives serial data on the sda input and checks for valid address and control information. if the appropriate slave address is set for the device, the device issues an acknowledge pulse and prepares to receive register address and data. data transmission is completed by either the reception of a stop condition or the reception of the data word sent to the device. a stop condition is recognized as a low to high transition of the sda input during the high portion of the scl signal. all other transitions of the sda line must occur during the low portion of the scl signal. an acknowledge issues after the reception of valid slave address, register-address, and data words. the i 2 c interfaces auto-sequence through register addresses, so that multiple data words can be sent for a given i 2 c transmission. reference figure 4-21 and figure 4-22 for details. top: master writes data to slave bottom: master reads data from slave figure 4-21. i 2 c data protocol from master to slave r read (high) w write (low) s start p stop from slave to master a acknowledge a not acknowledge s s w w a a a a a a a s p a p slave address register address data regaddr data regaddr data subaddr+n+1 data subaddr+n data regaddr+n+1 data regaddr+n register address slave address slave address n bytes + ack n bytes + ack a r a a s a6 a5 a4 a3 a2 a1 a0 r/nw a s7 s6 s5 s4 s3 s2 s1 s0 a d7 d6 d5 d4 d3 d2 d1 d0 a p s r/nw a p d7 d0 s7 s0 a6 a0 ... ... ... slave address + r/nw register address data data subaddress device address acknowledge stop condition start condition read, not write
37 TPS65216 www.ti.com slds187 ? october 2018 submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated figure 4-22. i 2 c protocol and transmission timing; i 2 c start/stop/acknowledge protocol figure 4-23. i 2 c protocol and transmission timing; i 2 c data transmission timing s p sda scl start stop address r/w ack ack ack/nack data data 1-7 8 9 1-7 8 9 1-7 8 9 s p sr s sda scl t f t f t r t r t low t high t sp t buf t su;sto t su;sta t su;dat t hd;dat t hd;sta t hd;sta
38 TPS65216 slds187 ? october 2018 www.ti.com submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated 4.4 device functional modes 4.4.1 modes of operation figure 4-24. modes of operation diagram 4.4.2 off in off mode, the pmic is completely shut down with the exception of a few circuits to monitor the ac_det, pwr_en and pb input. all power rails are turned off and the registers are reset to their default values. the i 2 c communication interface is turned off. this is the lowest-power mode of operation. to exit off mode v in_bias must exceed the uvlo threshold and one of the following wake-up events must occur: ? the pb input is pulled low. off active no power v in_bias > (v uvlo + hysteresis) & (pb ( ; ) || ac_det ( ; ) || pwr_en = high) pwr_en = high || ac_det ( ; ) || pb ( ; ) any state dcdc1..4 ldo1 int_ldo i 2 c pgood nwakeup registers pb low for > 8 s || ots || pgood fault ots external power removed seq down (500 ms) v in_bias > (v uvlo + hysteresis) recovery dcdc1..4 ldo1 int_ldo i 2 c pgood nwakeup dcdc1..4 ldo1 int_ldo i 2 c pgood nwakeup registers wait_pwr_en dcdc1..4 ldo1 int_ldo i 2 c pgood nwakeup pwr_en = high 20 s time-out & pb = high & pwr_en = low seq down (500 ms) suspend dcdc1..4 ldo1 int_ldo i 2 c pgood nwakeup dcdc1 reg. dcdc2 reg. dcdc1 = on || dcdc2 = on || dcdc3 = on || dcdc4 = on || ldo1 = on dcdc1..4 = off & ldo1 = off pwr_en = low any state v in_bias < v uvlo || (offnpfo = 1 & v pfi < power-fail threshold) seq down (500 ms) pre_off v in_bias > (v uvlo + hysteresis) & pb = high & ac_det = high & pwr_en = low v in_bias > (v uvlo + hysteresis) & (pb ( ; ) || ac_det ( ; ) || pwr_en = high) dcdc1..4 ldo1 int_ldo i 2 c pgood nwakeup registers = off = off = on = no = low = low : ghidxow = seq. dependent = seq. dependent = on = yes = low = hiz : ghidxow : ghidxow = on = on = on = yes = high (rail dependent) = hiz = on = on = on = yes = high (rail dependent) = low = off = off = off = no = low = low : ghidxow = off = off = on = no = low = hiz : ghidxow
39 TPS65216 www.ti.com slds187 ? october 2018 submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated ? the ac_det input is pulled low. ? the pwr_en input is pulled high. to enter off state, ensure all power rails are assigned to e sequencer, then pull the pwr_en pin low. additionally, if the offnpfo bit is set to 1b and the pfi input falls below the power fail threshold the device transitions to the off state. if a pgood or ots fault occurs while in the active state, TPS65216 will transition to the reset state. 4.4.3 active this is the typical mode of operation when the system is up and running. all dcdc converters, ldos, and load switch are operational and can be controlled through the i 2 c interface. after a wake-up event, the pmic enables all rails controlled by the sequencer and pulls the nwakeup pin low to signal the event to the host processor. the device only enters active state if the host asserts the pwr_en pin within 20 s after the wake-up event. otherwise it will enter off state. the nwakeup pin returns to hiz mode after the pwr_en pin is asserted. active state can also be directly entered from suspend state by pulling the pwr_en pin high. see suspend state description for details. to exit active mode, the pwr_en pin must be pulled low. 4.4.4 suspend suspend state is a low-power mode of operation intended to support system standby. typically all power rails are turned off with the exception of any rail with an seq register set to 0h. to enter suspend state, pull the pwr_en pin low. all power rails controlled by the power-down sequencer are shut down, and after 500 ms the device enters suspend state. all rails not controlled by the power-down sequencer will maintain state. note that all register values are reset as the device enters the suspend state. the device enters active state after it detects a wake-up event as described in the previous sections. 4.4.5 reset the TPS65216 can be reset by holding the pb pin low for more than 8 or 15 s, depending on the value of the trst bit. all rails are shut down by the sequencer and all register values reset to their default values. rails not controlled by the sequencer are shut down additionally. note that the reset function power- cycles the device and only temporarily shuts down the output rails. resetting the device does not lead to off state. if the pb_in pin is kept low for an extended amount of time, the device continues to cycle between active and reset state, entering reset every 8 or 15 s. the device is also reset if a pgood or ots fault occurs. the TPS65216 remains in the recovery state until the fault is removed, at which time it transitions back to the active state.
40 TPS65216 slds187 ? october 2018 www.ti.com submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated 4.5 register maps 4.5.1 password protection registers 0x11h through 0x26h are protected against accidental write by a 8-bit password. the password must be written prior to writing to a protected register and automatically resets to 0x00h after the next i 2 c transaction, regardless of the register accessed or transaction type (read or write). the password is required for write access only and is not required for read access. to write to a protected register: 1. write the address of the destination register, xored with the protection password (0x7dh), to the password register (0x10h). 2. write the data to the password protected register. 3. if the content of the password register xored with the address send matches 0x7dh, the data transfers to the protected register. otherwise, the transaction is ignored. in either case the password register resets to 0x00 after the transaction. the cycle must be repeated for any other register that is level1 write protected. 4.5.2 flag register the flag register contains a bit for each power rail and gpo to keep track of the enable state of the rails while the system is suspended. the following rules apply to the flag register: ? the power-up default value for any flag bit is 0. ? flag bits are read-only and cannot be written to. ? upon entering a suspend state, the flag bits are set to same value as their corresponding enable bits. rails and gpos enabled in a suspend state have flag bits set to 1, while all other flag bits are set to 0. flag bits are not updated while in the suspend state or when exiting the suspend state. ? the flag register is static in wait_pwr_en and active state. the flag register reflects the enable state of dcdc1, 2, 3, 4, ldo1, and gpo1, 2, 3 during the last suspend state. the host processor reads the flag register to determine if the system powered up from the off or suspend state. in the suspend state, typically the ddr memory is kept in self refresh mode and therefore the dc3_flg or dc4_flg bits are set.
41 TPS65216 www.ti.com slds187 ? october 2018 submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated 4.5.3 TPS65216registers table 4-5 lists the memory-mapped registers for the TPS65216. all register offset addresses not listed in table 4-5 should be considered as reserved locations and the register contents should not be modified. table 4-5. TPS65216 registers subaddress acronym register name r/w password protected section 0x0 chipid chip id r no go 0x1 int1 interrupt 1 r no go 0x2 int2 interrupt 2 r no go 0x3 int_mask1 interrupt mask 1 r/w no go 0x4 int_mask2 interrupt mask 2 r/w no go 0x5 status status r no go 0x6 control control r/w no go 0x7 flag flag r no go 0x10 password password r/w no go 0x11 enable1 enable 1 r/w yes go 0x12 enable2 enable 2 r/w yes go 0x13 config1 configuration 1 r/w yes go 0x14 config2 configuration 2 r/w yes go 0x15 config3 configuration 3 r/w yes go 0x16 dcdc1 dcdc1 control r/w yes go 0x17 dcdc2 dcdc2 control r/w yes go 0x18 dcdc3 dcdc3 control r/w yes go 0x19 dcdc4 dcdc4 control r/w yes go 0x1a slew slew rate control r/w yes go 0x1b ldo1 ldo1 control r/w yes go 0x20 seq1 sequencer 1 r/w yes go 0x21 seq2 sequencer 2 r/w yes go 0x22 seq3 sequencer 3 r/w yes go 0x23 seq4 sequencer 4 r/w yes go 0x24 seq5 sequencer 5 r/w yes go 0x25 seq6 sequencer 6 r/w yes go 0x26 seq7 sequencer 7 r/w yes go table 4-6 explains the common abbreviations used in this section. table 4-6. common abbreviations abbreviation description r read w write r/w read and write capable e2 backed by eeprom h hexadecimal notation of a group of bits b hexadecimal notation of a bit or group of bits x don't care reset value
42 TPS65216 slds187 ? october 2018 www.ti.com submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated 4.5.3.1 chipid register (subaddress = 0x0) [reset = 0x5] chipid is shown in figure 4-25 and described in table 4-7 . return to summary table . figure 4-25. chipid register 7 6 5 4 3 2 1 0 chip rev r-0h r-5h table 4-7. chipid register field descriptions bit field type reset description 7-3 chip r 0h chip id 0h = TPS65216 1h = future use ... 1fh = future use 2-0 rev r 5h revision code 0h = revision 1.0 1h = revision 1.1 2h = revision 2.0 3h = revision 2.1 4h = revision 3.0 5h = revision 4.0 (d0) 6h = future use 7h = future use
43 TPS65216 www.ti.com slds187 ? october 2018 submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated 4.5.3.2 int1 register (subaddress = 0x1) [reset = 0x0] int1 is shown in figure 4-26 and described in table 4-8 . return to summary table . figure 4-26. int1 register 7 6 5 4 3 2 1 0 reserved vprg ac pb hot reserved prgc r-0h r-0b r-0b r-0b r-0b r-0b r-0b table 4-8. int1 register field descriptions bit field type reset description 7-6 reserved r 0h 5 vprg r 0b programming voltage interrupt 0b = no significance 1b = input voltage is too low for programming power-up default values. 4 ac r 0b ac_det pin status change interrupt. note: status information is available in status register 0b = no change in status 1b = ac_det status change (ac_det pin changed high to low or low to high) 3 pb r 0b push-button status change interrupt. note: status information is available in status register 0b = no change in status 1b = push-button status change (pb changed high to low or low to high) 2 hot r 0b thermal shutdown early warning 0b = chip temperature is below hot threshold 1b = chip temperature exceeds hot threshold 1 reserved r 0b 0 prgc r 0b eeprom programming complete interrupt 0b = no significance 1b = programming of power-up default settings has completed successfully
44 TPS65216 slds187 ? october 2018 www.ti.com submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated 4.5.3.3 int2 register (subaddress = 0x2) [reset = 0x0] int2 is shown in figure 4-27 and described in table 4-9 . return to summary table . figure 4-27. int2 register 7 6 5 4 3 2 1 0 reserved ls_f reserved reserved ls_i reserved reserved r-0h r-0b r-0b r-0b r-0b r-0b r-0b table 4-9. int2 register field descriptions bit field type reset description 7-6 reserved r 0h 5 ls_f r 0b load switch fault interrupt 0b = no fault. switch is working normally. 1b = load switch exceeded operating temperature limit and is temporarily disabled. 4 reserved r 0b 3 reserved r 0b 2 ls_i r 0b load switch current-limit interrupt 0b = load switch is disabled or not in current limit 1b = load switch is actively limiting the output current (output load is exceeding current limit value) 1 reserved r 0b 0 reserved r 0b
45 TPS65216 www.ti.com slds187 ? october 2018 submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated 4.5.3.4 int_mask1 register (subaddress = 0x3) [reset = 0x0] int_mask1 is shown in figure 4-28 and described in table 4-10 . return to summary table . figure 4-28. int_mask1 register 7 6 5 4 3 2 1 0 reserved vprgm acm pbm hotm reserved prgcm r-0h r/w-0b r/w-0b r/w-0b r/w-0b r/w-0b r/w-0b table 4-10. int_mask1 register field descriptions bit field type reset description 7-6 reserved r 0h 5 vprgm r/w 0b programming voltage interrupt mask bit. note: mask bit has no effect on monitoring function 0b = interrupt is unmasked (interrupt event pulls nint pin low) 1b = interrupt is masked (interrupt has no effect on nint pin) 4 acm r/w 0b ac_det interrupt masking bit. 0b = interrupt is unmasked (interrupt event pulls nint pin low) 1b = interrupt is masked (interrupt has no effect on nint pin) note: mask bit has no effect on monitoring function 3 pbm r/w 0b pb interrupt masking bit. note: mask bit has no effect on monitoring function 0b = interrupt is unmasked (interrupt event pulls nint pin low) 1b = interrupt is masked (interrupt has no effect on nint pin) 2 hotm r/w 0b hot interrupt masking bit. note: mask bit has no effect on monitoring function 0b = interrupt is unmasked (interrupt event pulls nint pin low) 1b = interrupt is masked (interrupt has no effect on nint pin) 1 reserved r/w 0b 0 prgcm r/w 0b prgc interrupt masking bit. note: mask bit has no effect on monitoring function 0b = interrupt is unmasked (interrupt event pulls nint pin low) 1b = interrupt is masked (interrupt has no effect on nint pin)
46 TPS65216 slds187 ? october 2018 www.ti.com submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated 4.5.3.5 int_mask2 register (subaddress = 0x4) [reset = 0x0] int_mask2 is shown in figure 4-29 and described in table 4-11 . return to summary table . figure 4-29. int_mask2 register 7 6 5 4 3 2 1 0 reserved ls_fm reserved reserved ls_im reserved reserved r-0h r/w-0b r/w-0b r/w-0b r/w-0b r/w-0b r/w-0b table 4-11. int_mask2 register field descriptions bit field type reset description 7-6 reserved r 0h 5 ls_fm r/w 0b ls fault interrupt mask bit. note: mask bit has no effect on monitoring function 0b = interrupt is unmasked (interrupt event pulls nint pin low) 1b = interrupt is masked (interrupt has no effect on nint pin) 4 reserved r/w 0b 3 reserved r/w 0b 2 ls_im r/w 0b ls current-limit interrupt mask bit. note: mask bit has no effect on monitoring function 0b = interrupt is unmasked (interrupt event pulls nint pin low) 1b = interrupt is masked (interrupt has no effect on nint pin) 1 reserved r/w 0b 0 reserved r/w 0b
47 TPS65216 www.ti.com slds187 ? october 2018 submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated 4.5.3.6 status register (subaddress = 0x5) [reset = 00xxxxxxb] register mask: c0h status is shown in figure 4-30 and described in table 4-12 . return to summary table . figure 4-30. status register 7 6 5 4 3 2 1 0 reserved ee ac_state pb_state state reserved r-0b r-0b r-x r-x r-x r-x table 4-12. status register field descriptions bit field type reset description 7 reserved r 0b 6 ee r 0b eeprom status 0b = eeprom values have not been changed from factory default setting 1b = eeprom values have been changed from factory default settings 5 ac_state r x ac_det input status bit 0b = ac_det input is inactive (ac_det input pin is high) 1b = ac_det input is active (ac_det input is low) 4 pb_state r x pb input status bit 0b = push button input is inactive (pb input pin is high) 1b = push button input is active (pb input pin is low) 3-2 state r x state machine state indication 0h = pmic is in transitional state 1h = pmic is in wait_pwr_en state 2h = pmic is in active state 3h = pmic is in suspend state 1-0 reserved r x
48 TPS65216 slds187 ? october 2018 www.ti.com submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated 4.5.3.7 control register (subaddress = 0x6) [reset = 0x0] control is shown in figure 4-31 and described in table 4-13 . return to summary table . figure 4-31. control register 7 6 5 4 3 2 1 0 reserved offnpfo reserved r-0h r/w-0b r/w-0b table 4-13. control register field descriptions bit field type reset description 7-2 reserved r 0h 1 offnpfo r/w 0h power-fail shutdown bit 0b = npfo has no effect on pmic state 1b = all rails are shut down and pmic enters off state when pfi comparator trips (npfo is low) 0 reserved r/w 0h
49 TPS65216 www.ti.com slds187 ? october 2018 submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated 4.5.3.8 flag register (subaddress = 0x7) [reset = 0x0] flag is shown in figure 4-32 and described in table 4-14 . return to summary table . figure 4-32. flag register 7 6 5 4 3 2 1 0 gpo2_flg reserved gpo1_flg ldo1_flg dc4_flg dc3_flg dc2_flg dc1_flg r-0b r-0b r-0b r-0b r-0b r-0b r-0b r-0b table 4-14. flag register field descriptions bit field type reset description 7 gpo2_flg r 0b gpo2 flag bit 0b = device powered up from off or suspend state and gpo2 was disabled while in suspend. 1b = device powered up from suspend state and gpo2 was enabled while in suspend. 6 reserved r 0b 5 gpo1_flg r 0b gpo1 flag bit 0b = device powered up from off or suspend state and gpo1 was disabled while in suspend. 1b = device powered up from suspend state and gpo1 was enabled while in suspend. 4 ldo1_flg r 0b ldo1 flag bit 0b = device powered up from off or suspend state and ldo1 was disabled while in suspend. 1b = device powered up from suspend state and ldo1 was enabled while in suspend. 3 dc4_flg r 0b dcdc4 flag bit 0b = device powered up from off or suspend state and dcdc4 was disabled while in suspend. 1b = device powered up from suspend state and dcdc4 was enabled while in suspend. 2 dc3_flg r 0b dcdc3 flag bit 0b = device powered up from off or suspend state and dcdc3 was disabled while in suspend. 1b = device powered up from suspend state and dcdc3 was enabled while in suspend. 1 dc2_flg r 0b dcdc2 flag bit 0b = device powered up from off or suspend state and dcdc2 was disabled while in suspend. 1b = device powered up from suspend state and dcdc2 was enabled while in suspend. 0 dc1_flg r 0b dcdc1 flag bit 0b = device powered up from off or suspend state and dcdc1 was disabled while in suspend. 1b = device powered up from suspend state and gdcdc1po3 was enabled while in suspend.
50 TPS65216 slds187 ? october 2018 www.ti.com submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated 4.5.3.9 password register (subaddress = 0x10) [reset = 0x0] password is shown in figure 4-33 and described in table 4-15 . return to summary table . figure 4-33. password register 7 6 5 4 3 2 1 0 pwrd r/w-0h table 4-15. password register field descriptions bit field type reset description 7-0 pwrd r/w 0h register is used for accessing password protected registers (see section 4.5.1 for details). breaking the freshness seal (see for details).programming power-up default values (see for details). read-back always yields 0x00.
51 TPS65216 www.ti.com slds187 ? october 2018 submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated 4.5.3.10 enable1 register (subaddress = 0x11) [reset = 0x0] enable1 is shown in figure 4-34 and described in table 4-16 . return to summary table . password protected. figure 4-34. enable1 register 7 6 5 4 3 2 1 0 reserved reserved reserved dc4_en dc3_en dc2_en dc1_en r-0h r/w-0b r/w-0b r/w-0b r/w-0b r/w-0b r/w-0b table 4-16. enable1 register field descriptions bit field type reset description 7-6 reserved r 0h 5 reserved r/w 0b 4 reserved r/w 0b 3 dc4_en r/w 0b dcdc4 enable bit. note: at power-up/down this bit is automatically updated by the internal power sequencer. 0b = disabled 1b = enabled 2 dc3_en r/w 0b dcdc3 enable bit. note: at power-up/down this bit is automatically updated by the internal power sequencer. 0b = disabled 1b = enabled 1 dc2_en r/w 0b dcdc2 enable bit. note: at power-up/down this bit is automatically updated by the internal power sequencer. 0b = disabled 1b = enabled 0 dc1_en r/w 0b dcdc1 enable bit. note: at power-up/down this bit is automatically updated by the internal power sequencer. 0b = disabled 1b = enabled
52 TPS65216 slds187 ? october 2018 www.ti.com submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated 4.5.3.11 enable2 register (subaddress = 0x12) [reset = 0x0] enable2 is shown in figure 4-35 and described in table 4-17 . return to summary table . password protected. figure 4-35. enable2 register 7 6 5 4 3 2 1 0 reserved gpio2 reserved gpio1 ls_en reserved reserved ldo1_en r-0b r/w-0b r/w-0b r/w-0b r/w-0b r/w-0b r/w-0b r/w-0b table 4-17. enable2 register field descriptions bit field type reset description 7 reserved r 0b 6 gpio2 r/w 0b general purpose output 3 / reset polarity. note: if dc12_rst bit (register 0x14) is set to 1 this bit has no function. 0b = gpio2 output is driven low 1b = gpio2 output is hiz 5 reserved r/w 0b 4 gpio1 r/w 0b general purpose output 1. note: if io_sel bit (register 0x13) is set to 1 this bit has no function. 0b = gpo1 output is driven low 1b = gpo1 output is hiz 3 ls_en r/w 0b load switch (ls) enable bit 0b = disabled 1b = enabled 2 reserved r/w 0b 1 reserved r/w 0b 0 ldo1_en r/w 0b ldo1 enable bit. 0b = disabled 1b = enabled note: at power-up/down this bit is automatically updated by the internal power sequencer.
53 TPS65216 www.ti.com slds187 ? october 2018 submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated 4.5.3.12 config1 register (subaddress = 0x13) [reset = 0x4c] config1 is shown in figure 4-36 and described in table 4-18 . return to summary table . password protected. figure 4-36. config1 register 7 6 5 4 3 2 1 0 trst reserved reserved pgdly strict uvlo r/w-0b r/w-1b r/w-0b r/w-1h r/w-1b r/w-0h table 4-18. config1 register field descriptions bit field type reset description 7 trst r/w , e2 0b push-button reset time constant 0b = 8s 1b = 15s 6 reserved r/w 1b 5 reserved r/w 0b 4-3 pgdly r/w , e2 1h power-good delay. note: power-good delay applies to rising-edge only (power-up), not falling edge (power-down or fault) 0h = 10 ms 1h = 20 ms 2h = 50 ms 3h = 150 ms 2 strict r/w , e2 1b supply voltage supervisor sensitivity selection. see section 3.5 for details. 0b = power-good threshold (vout falling) has wider limits. overvoltage is not monitored 1b = power-good threshold (vout falling) has tight limits. overvoltage is monitored. 1-0 uvlo r/w , e2 0h uvlo setting 0h = 2.75 v 1h = 2.95 v 2h = 3.25 v 3h = 3.35 v
54 TPS65216 slds187 ? october 2018 www.ti.com submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated 4.5.3.13 config2 register (subaddress = 0x14) [reset = 0xc0] config2 is shown in figure 4-37 and described in table 4-19 . return to summary table . password protected. figure 4-37. config2 register 7 6 5 4 3 2 1 0 dc12_rst uvlohys reserved lsilim reserved r/w-1b r/w-1b r-0h r/w-0h r/w-0h table 4-19. config2 register field descriptions bit field type reset description 7 dc12_rst r/w 1b , e2 dcdc1 and dcdc2 reset-pin enable 0b = gpio2 is configured as general-purpose output 1b = gpio2 is configured as warm-reset input to dcdc1 and dcdc2 6 uvlohys r/w 1b , e2 uvlo hysteresis 0b = 200 mv 1b = 400 mv 5-4 reserved r 0h 3-2 lsilim r/w 0h load switch (ls) current limit selection 0h = 100 ma, (min = 98 ma) 1h = 200 ma, (min = 194 ma) 2h = 500 ma, (min = 475 ma) 3h = 1000 ma, (min = 900 ma) see the ls current limit specification in section 3.5 for more details. 1-0 reserved r/w 0h
55 TPS65216 www.ti.com slds187 ? october 2018 submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated 4.5.3.14 config3 register (subaddress = 0x15) [reset = 0x0] config3 is shown in figure 4-38 and described in table 4-20 . return to summary table . password protected. figure 4-38. config3 register 7 6 5 4 3 2 1 0 reserved lsnpfo reserved reserved lsdchrg reserved reserved r-0h r/w-0b r/w-0b r/w-0b r/w-0b r/w-0b r/w-0b table 4-20. config3 register field descriptions bit field type reset description 7-6 reserved r 0b 5 lsnpfo r/w 0b load switch power-fail disable bit 0b = load switch status is not affected by power-fail comparator 1b = load switch is disabled if power-fail comparator trips (npfo is low) 4 reserved r/w 0b 3 reserved r/w 0b 2 lsdchrg r/w 0b load switch discharge enable bit 0b = active discharge is disabled 1b = active discharge is enabled (load switch output is actively discharged when switch is off) 1 reserved r/w 0b 0 reserved r/w 0b
56 TPS65216 slds187 ? october 2018 www.ti.com submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated 4.5.3.15 dcdc1 register (offset = 0x16) [reset = 0x99] dcdc1 is shown in figure 4-39 and described in table 4-21 . return to summary table . note 1: this register is password protected. for more information, see section 4.5.1 . note 2: a 5-ms blanking time of the overvoltage and undervoltage monitoring occurs when a write is performed on the dcdc1 register. note 3: to change the output voltage of dcdc1, the go bit or the godsbl bit must be set to 1b in register 0x1a. figure 4-39. dcdc1 register 7 6 5 4 3 2 1 0 pfm reserved dcdc1 r/w-1b r-0b r/w-19h table 4-21. dcdc1 register field descriptions bit field type reset description 7 pfm r/w 1b pulse frequency modulation (pfm, also known as pulse-skip-mode) enable. pfm mode improves light-load efficiency. actual pfm mode operation depends on load condition. 0b = disabled (forced pwm) 1b = enabled 6 reserved r 0b
57 TPS65216 www.ti.com slds187 ? october 2018 submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated table 4-21. dcdc1 register field descriptions (continued) bit field type reset description 5-0 dcdc1 r/w , e2 19h dcdc1 output voltage setting 0h = 0.850 1h = 0.860 2h = 0.870 3h = 0.880 4h = 0.890 5h = 0.900 6h = 0.910 7h = 0.920 8h = 0.930 9h = 0.940 ah = 0.950 bh = 0.960 ch = 0.970 dh = 0.980 eh = 0.990 fh = 1.000 10h = 1.010 11h = 1.020 12h = 1.030 13h = 1.040 14h = 1.050 15h = 1.060 16h = 1.070 17h = 1.080 18h = 1.090 19h = 1.100 1ah = 1.110 1bh = 1.120 1ch = 1.130 1dh = 1.140 1eh = 1.150 1fh = 1.160 20h = 1.170 21h = 1.180 22h = 1.190 23h = 1.200
58 TPS65216 slds187 ? october 2018 www.ti.com submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated table 4-21. dcdc1 register field descriptions (continued) bit field type reset description 24h = 1.210 25h = 1.220 26h = 1.230 27h = 1.240 28h = 1.250 29h = 1.260 2ah = 1.270 2bh = 1.280 2ch = 1.290 2dh = 1.300 2eh = 1.310 2fh = 1.320 30h = 1.330 31h = 1.340 32h = 1.350 33h = 1.375 34h = 1.400 35h = 1.425 36h = 1.450 37h = 1.475 38h = 1.500 39h = 1.525 3ah = 1.550 3bh = 1.575 3ch = 1.600 3dh = 1.625 3eh = 1.650 3fh = 1.675
59 TPS65216 www.ti.com slds187 ? october 2018 submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated 4.5.3.16 dcdc2 register (subaddress = 0x17) [reset = 0x99] dcdc2 is shown in figure 4-40 and described in table 4-22 . return to summary table . note 1: this register is password protected. for more information, see section 4.5.1 . note 2: a 5-ms blanking time of the overvoltage and undervoltage monitoring occurs when a write is performed on the dcdc2 register. note 3: to change the output voltage of dcdc2, the go bit or the godsbl bit must be set to 1b in register 0x1a. figure 4-40. dcdc2 register 7 6 5 4 3 2 1 0 pfm reserved dcdc2 r/w-1b r-0b r/w-19h table 4-22. dcdc2 register field descriptions bit field type reset description 7 pfm r/w 1b pulse frequency modulation (pfm, also known as pulse-skip-mode) enable. pfm mode improves light-load efficiency. actual pfm mode operation depends on load condition. 0b = disabled (forced pwm) 1b = enabled 6 reserved r 0b
60 TPS65216 slds187 ? october 2018 www.ti.com submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated table 4-22. dcdc2 register field descriptions (continued) bit field type reset description 5-0 dcdc2 r/w , e2 19h dcdc2 output voltage setting 0h = 0.850 1h = 0.860 2h = 0.870 3h = 0.880 4h = 0.890 5h = 0.900 6h = 0.910 7h = 0.920 8h = 0.930 9h = 0.940 ah = 0.950 bh = 0.960 ch = 0.970 dh = 0.980 eh = 0.990 fh = 1.000 10h = 1.010 11h = 1.020 12h = 1.030 13h = 1.040 14h = 1.050 15h = 1.060 16h = 1.070 17h = 1.080 18h = 1.090 19h = 1.100 1ah = 1.110 1bh = 1.120 1ch = 1.130 1dh = 1.140 1eh = 1.150 1fh = 1.160 20h = 1.170 21h = 1.180 22h = 1.190 23h = 1.200
61 TPS65216 www.ti.com slds187 ? october 2018 submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated table 4-22. dcdc2 register field descriptions (continued) bit field type reset description 24h = 1.210 25h = 1.220 26h = 1.230 27h = 1.240 28h = 1.250 29h = 1.260 2ah = 1.270 2bh = 1.280 2ch = 1.290 2dh = 1.300 2eh = 1.310 2fh = 1.320 30h = 1.330 31h = 1.340 32h = 1.350 33h = 1.375 34h = 1.400 35h = 1.425 36h = 1.450 37h = 1.475 38h = 1.500 39h = 1.525 3ah = 1.550 3bh = 1.575 3ch = 1.600 3dh = 1.625 3eh = 1.650 3fh = 1.675
62 TPS65216 slds187 ? october 2018 www.ti.com submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated 4.5.3.17 dcdc3 register (subaddress = 0x18) [reset = 0x8c] dcdc3 is shown in figure 4-41 and described in table 4-23 . return to summary table . note 1: this register is password protected. for more information, see section 4.5.1 . note 2: a 5-ms blanking time of the overvoltage and undervoltage monitoring occurs when a write is performed on the dcdc3 register. note power-up default may differ depending on rsel value. see section 4.3.1.10 for details. figure 4-41. dcdc3 register 7 6 5 4 3 2 1 0 pfm reserved dcdc3 r/w-1b r-0b r/w-ch table 4-23. dcdc3 register field descriptions bit field type reset description 7 pfm r/w 1b pulse frequency modulation (pfm, also known as pulse-skip-mode) enable. pfm mode improves light-load efficiency. actual pfm mode operation depends on load condition. 0b = disabled (forced pwm) 1b = enabled 6 reserved r 0b
63 TPS65216 www.ti.com slds187 ? october 2018 submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated table 4-23. dcdc3 register field descriptions (continued) bit field type reset description 5-0 dcdc3 r/w , e2 ch dcdc3 output voltage setting 0h = 0.900 1h = 0.925 2h = 0.950 3h = 0.975 4h = 1.000 5h = 1.025 6h = 1.050 7h = 1.075 8h = 1.100 9h = 1.125 ah = 1.150 bh = 1.175 ch = 1.200 dh = 1.225 eh = 1.250 fh = 1.275 10h = 1.300 11h = 1.325 12h = 1.350 13h = 1.375 14h = 1.400 15h = 1.425 16h = 1.450 17h = 1.475 18h = 1.500 19h = 1.525 1ah = 1.550 1bh = 1.600 1ch = 1.650 1dh = 1.700 1eh = 1.750 1fh = 1.800 20h = 1.850 21h = 1.900 22h = 1.950 23h = 2.000
64 TPS65216 slds187 ? october 2018 www.ti.com submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated table 4-23. dcdc3 register field descriptions (continued) bit field type reset description 24h = 2.050 25h = 2.100 26h = 2.150 27h = 2.200 28h = 2.250 29h = 2.300 2ah = 2.350 2bh = 2.400 2ch = 2.450 2dh = 2.500 2eh = 2.550 2fh = 2.600 30h = 2.650 31h = 2.700 32h = 2.750 33h = 2.800 34h = 2.850 35h = 2.900 36h = 2.950 37h = 3.000 38h = 3.050 39h = 3.100 3ah = 3.150 3bh = 3.200 3ch = 3.250 3dh = 3.300 3eh = 3.350 3fh = 3.400
65 TPS65216 www.ti.com slds187 ? october 2018 submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated 4.5.3.18 dcdc4 register (subaddress = 0x19) [reset = 0xb2] dcdc4 is shown in figure 4-42 and described in table 4-24 . return to summary table . note 1: this register is password protected. for more information, see section 4.5.1 . note 2: a 5-ms blanking time of the overvoltage and undervoltage monitoring occurs when a write is performed on the dcdc4 register. note power-up default may differ depending on rsel value. see section 4.3.1.10 for details. the reserved setting should not be selected and the output voltage settings should not be modified while the converter is operating. figure 4-42. dcdc4 register 7 6 5 4 3 2 1 0 pfm reserved dcdc4 r/w-1b r-0b r/w-32h table 4-24. dcdc4 register field descriptions bit field type reset description 7 pfm r/w 1b pulse frequency modulation (pfm, also known as pulse-skip-mode) enable. pfm mode improves light-load efficiency. actual pfm mode operation depends on load condition. 0b = disabled (forced pwm) 1b = enabled 6 reserved r 0b
66 TPS65216 slds187 ? october 2018 www.ti.com submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated table 4-24. dcdc4 register field descriptions (continued) bit field type reset description 5-0 dcdc4 r/w , e2 32h dcdc4 output voltage setting 0h = 1.175 1h = 1.200 2h = 1.225 3h = 1.250 4h = 1.275 5h = 1.300 6h = 1.325 7h = 1.350 8h = 1.375 9h = 1.400 ah = 1.425 bh = 1.450 ch = 1.475 dh = 1.500 eh = 1.525 fh = 1.550 10h = 1.600 11h = 1.650 12h = 1.700 13h = 1.750 14h = 1.800 15h = 1.850 16h = 1.900 17h = 1.950 18h = 2.000 19h = 2.050 1ah = 2.100 1bh = 2.150 1ch = 2.200 1dh = 2.250 1eh = 2.300 1fh = 2.3500 20h = 2.400 21h = 2.450 22h = 2.500 23h = 2.550
67 TPS65216 www.ti.com slds187 ? october 2018 submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated table 4-24. dcdc4 register field descriptions (continued) bit field type reset description 24h = 2.600 25h = 2.650 26h = 2.700 27h = 2.750 28h = 2.800 29h = 2.850 2ah = 2.900 2bh = 2.950 2ch = 3.000 2dh = 3.050 2eh = 3.100 2fh = 3.150 30h = 3.200 31h = 3.250 32h = 3.300 33h = 3.350 34h = 3.400 35h = reserved 36h = reserved 37h = reserved 38h = reserved 39h = reserved 3ah = reserved 3bh = reserved 3ch = reserved 3dh = reserved 3eh = reserved 3fh = reserved
68 TPS65216 slds187 ? october 2018 www.ti.com submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated 4.5.3.19 slew register (subaddress = 0x1a) [reset = 0x6] slew is shown in figure 4-43 and described in table 4-25 . return to summary table . note slew-rate control applies to dcdc1 and dcdc2 only. if changing from a higher voltage to lower voltage while strict = 1 and converters are in a no load state, pfm bit for dcdc1 and dcdc2 must be set to 0. figure 4-43. slew register 7 6 5 4 3 2 1 0 go godsbl reserved slew r/w-0b r/w-0b r-0h r/w-6h table 4-25. slew register field descriptions bit field type reset description 7 go r/w 0b go bit. note: bit is automatically reset at the end of the voltage transition 0b = no change 1b = initiates the transition from present state to the output voltage setting currently stored in dcdc1 / dcdc2 register. slew setting does apply. 6 godsbl r/w 0b go disable bit 0b = enabled 1b = disabled; dcdc1 and dcdc2 output voltage changes whenever set-point is updated in dcdc1 / dcdc2 register without having to write to the go bit. slew setting does apply. 5-3 reserved r 0h 2-0 slew r/w 6h output slew rate setting 0h = 160 s/step (0.0625 mv/ s at 10 mv per step) 1h = 80 s/step (0.125 mv/ s at 10 mv per step) 2h = 40 s/step (0.250 mv/ s at 10 mv per step) 3h = 20 s/step (0.500 mv/ s at 10 mv per step) 4h = 10 s/step (1.0 mv/ s at 10 mv per step) 5h = 5 s/step (2.0 mv/ s at 10 mv per step) 6h = 2.5 s/step (4.0 mv/ s at 10 mv per step) 7h = immediate; slew rate is only limited by control loop response time. note: the actual slew rate depends on the voltage step per code. refer to dcdcx registers for details.
69 TPS65216 www.ti.com slds187 ? october 2018 submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated 4.5.3.20 ldo1 register (subaddress = 0x1b) [reset = 0x1f] ldo1 is shown in figure 4-44 and described in table 4-26 . return to summary table . note 1: this register is password protected. for more information, see section 4.5.1 . note 2: a 5-ms blanking time of the overvoltage and undervoltage monitoring occurs when a write is performed on the ldo1 register. figure 4-44. ldo1 register 7 6 5 4 3 2 1 0 reserved ldo1 r-0h r/w-1fh table 4-26. ldo1 register field descriptions bit field type reset description 7-6 reserved r 0h 5-0 ldo1 r/w , e2 1fh ldo1 output voltage setting 0h = 0.900 1h = 0.925 2h = 0.950 3h = 0.975 4h = 1.000 5h = 1.025 6h = 1.050 7h = 1.075 8h = 1.100 9h = 1.125 ah = 1.150 bh = 1.175 ch = 1.200 dh = 1.225 eh = 1.250 fh = 1.275 10h = 1.300 11h = 1.325 12h = 1.350 13h = 1.375 14h = 1.400 15h = 1.425 16h = 1.450 17h = 1.475 18h = 1.500 19h = 1.525
70 TPS65216 slds187 ? october 2018 www.ti.com submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated table 4-26. ldo1 register field descriptions (continued) bit field type reset description 1ah = 1.550 1bh = 1.600 1ch = 1.650 1dh = 1.700 1eh = 1.750 1fh = 1.800 20h = 1.850 21h = 1.900 22h = 1.950 23h = 2.000 24h = 2.050 25h = 2.100 26h = 2.150 27h = 2.200 28h = 2.250 29h = 2.300 2ah = 2.350 2bh = 2.400 2ch = 2.450 2dh = 2.500 2eh = 2.550 2fh = 2.600 30h = 2.650 31h = 2.700 32h = 2.750 33h = 2.800 34h = 2.850 35h = 2.900 36h = 2.950 37h = 3.000 38h = 3.050 39h = 3.100 3ah = 3.150 3bh = 3.200 3ch = 3.250 3dh = 3.300 3eh = 3.350 3fh = 3.400
71 TPS65216 www.ti.com slds187 ? october 2018 submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated 4.5.3.21 seq1 register (subaddress = 0x20) [reset = 0x0] seq1 is shown in figure 4-45 and described in table 4-27 . return to summary table . password protected. figure 4-45. seq1 register 7 6 5 4 3 2 1 0 dly8 dly7 dly6 dly5 dly4 dly3 dly2 dly1 r/w-0b r/w-0b r/w-0b r/w-0b r/w-0b r/w-0b r/w-0b r/w-0b table 4-27. seq1 register field descriptions bit field type reset description 7 dly8 r/w , e2 0b delay8 (occurs after strobe8 and before strobe9) 0b = 2 ms 1b = 5 ms 6 dly7 r/w , e2 0b delay7 (occurs after strobe7 and before strobe8) 0b = 2 ms 1b = 5 ms 5 dly6 r/w , e2 0b delay6 (occurs after strobe6 and before strobe7) 0b = 2 ms 1b = 5 ms 4 dly5 r/w , e2 0b delay5 (occurs after strobe5 and before strobe6) 0b = 2 ms 1b = 5 ms 3 dly4 r/w , e2 0b delay4 (occurs after strobe4 and before strobe5) 0b = 2 ms 1b = 5 ms 2 dly3 r/w , e2 0b delay3 (occurs after strobe3 and before strobe4) 0b = 2 ms 1b = 5 ms 1 dly2 r/w , e2 0b delay2 (occurs after strobe2 and before strobe3) 0b = 2 ms 1b = 5 ms 0 dly1 r/w , e2 0b delay1 (occurs after strobe1 and before strobe2) 0b = 2 ms 1b = 5 ms
72 TPS65216 slds187 ? october 2018 www.ti.com submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated 4.5.3.22 seq2 register (subaddress = 0x21) [reset = 0x0] seq2 is shown in figure 4-46 and described in table 4-28 . return to summary table . password protected. figure 4-46. seq2 register 7 6 5 4 3 2 1 0 dlyfctr reserved dly9 r/w -0b r-0h r/w -0b table 4-28. seq2 register field descriptions bit field type reset description 7 dlyfctr r/w , e2 0b power-down delay factor 0b = 1x 1b = 10x (delay times are multiplied by 10x during power-down) note: dlyfctr has no effect on power-up timing. 6-1 reserved r 0h 0 dly9 r/w , e2 0b delay9 (occurs after strobe9 and before strobe10) 0b = 2 ms 1b = 5 ms
73 TPS65216 www.ti.com slds187 ? october 2018 submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated 4.5.3.23 seq3 register (subaddress = 0x22) [reset = 0x98] seq3 is shown in figure 4-47 and described in table 4-29 . return to summary table . password protected. figure 4-47. seq3 register 7 6 5 4 3 2 1 0 dc2_seq dc1_seq r/w-9h r/w-8h table 4-29. seq3 register field descriptions bit field type reset description 7-4 dc2_seq r/w , e2 9h dcdc2 enable strobe 0h = rail is not controlled by sequencer 1h = rail is not controlled by sequencer 2h = rail is not controlled by sequencer 3h = enable at strobe3 4h = enable at strobe4 5h = enable at strobe5 6h = enable at strobe6 7h = enable at strobe7 8h = enable at strobe8 9h = enable at strobe9 ah = enable at strobe10 bh = rail is not controlled by sequencer ch = rail is not controlled by sequencer dh = rail is not controlled by sequencer eh = rail is not controlled by sequencer fh = rail is not controlled by sequencer
74 TPS65216 slds187 ? october 2018 www.ti.com submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated table 4-29. seq3 register field descriptions (continued) bit field type reset description 3-0 dc1_seq r/w , e2 8h dcdc1 enable strobe 0h = rail is not controlled by sequencer 1h = rail is not controlled by sequencer 2h = rail is not controlled by sequencer 3h = enable at strobe3 4h = enable at strobe4 5h = enable at strobe5 6h = enable at strobe6 7h = enable at strobe7 8h = enable at strobe8 9h = enable at strobe9 ah = enable at strobe10 bh = rail is not controlled by sequencer ch = rail is not controlled by sequencer dh = rail is not controlled by sequencer eh = rail is not controlled by sequencer fh = rail is not controlled by sequencer
75 TPS65216 www.ti.com slds187 ? october 2018 submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated 4.5.3.24 seq4 register (subaddress = 0x23) [reset = 0x75] seq4 is shown in figure 4-48 and described in table 4-30 . return to summary table . password protected. figure 4-48. seq4 register 7 6 5 4 3 2 1 0 dc4_seq dc3_seq r/w-7h r/w-5h table 4-30. seq4 register field descriptions bit field type reset description 7-4 dc4_seq r/w , e2 7h dcdc4 enable strobe 0h = rail is not controlled by sequencer 1h = rail is not controlled by sequencer 2h = rail is not controlled by sequencer 3h = enable at strobe3 4h = enable at strobe4 5h = enable at strobe5 6h = enable at strobe6 7h = enable at strobe7 8h = enable at strobe8 9h = enable at strobe9 ah = enable at strobe10 bh = rail is not controlled by sequencer ch = rail is not controlled by sequencer dh = rail is not controlled by sequencer eh = rail is not controlled by sequencer fh = rail is not controlled by sequencer
76 TPS65216 slds187 ? october 2018 www.ti.com submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated table 4-30. seq4 register field descriptions (continued) bit field type reset description 3-0 dc3_seq r/w , e2 5h dcdc3 enable strobe 0h = rail is not controlled by sequencer 1h = rail is not controlled by sequencer 2h = rail is not controlled by sequencer 3h = enable at strobe3 4h = enable at strobe4 5h = enable at strobe5 6h = enable at strobe6 7h = enable at strobe7 8h = enable at strobe8 9h = enable at strobe9 ah = enable at strobe10 bh = rail is not controlled by sequencer ch = rail is not controlled by sequencer dh = rail is not controlled by sequencer eh = rail is not controlled by sequencer fh = rail is not controlled by sequencer
77 TPS65216 www.ti.com slds187 ? october 2018 submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated 4.5.3.25 seq5 register (subaddress = 0x24) [reset = 0x12] seq5 is shown in figure 4-49 and described in table 4-31 . return to summary table . password protected. figure 4-49. seq5 register 7 6 5 4 3 2 1 0 reserved reserved reserved reserved r-0h r/w-1h r-0h r/w-2h table 4-31. seq5 register field descriptions bit field type reset description 7-6 reserved r 0h 5-4 reserved r/w, e2 1h 3-2 reserved r 0h 1-0 reserved r/w, e2 2h
78 TPS65216 slds187 ? october 2018 www.ti.com submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated 4.5.3.26 seq6 register (subaddress = 0x25) [reset = 0x63] seq6 is shown in figure 4-50 and described in table 4-32 . return to summary table . password protected. figure 4-50. seq6 register 7 6 5 4 3 2 1 0 reserved ldo1_seq r/w-6h r/w-3h table 4-32. seq6 register field descriptions bit field type reset description 7-4 reserved r/w 6h reserved 3-0 ldo1_seq r/w , e2 3h ldo1 enable strobe 0h = rail is not controlled by sequencer 1h = rail is not controlled by sequencer 2h = rail is not controlled by sequencer 3h = enable at strobe3 4h = enable at strobe4 5h = enable at strobe5 6h = enable at strobe6 7h = enable at strobe7 8h = enable at strobe8 9h = enable at strobe9 ah = enable at strobe10 bh = rail is not controlled by sequencer ch = rail is not controlled by sequencer dh = rail is not controlled by sequencer eh = rail is not controlled by sequencer fh = rail is not controlled by sequencer
79 TPS65216 www.ti.com slds187 ? october 2018 submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated 4.5.3.27 seq7 register (subaddress = 0x26) [reset = 0x3] seq7 is shown in figure 4-51 and described in table 4-33 . return to summary table . password protected. figure 4-51. seq7 register 7 6 5 4 3 2 1 0 gpo2_seq gpo1_seq r/w-0h r/w-3h table 4-33. seq7 register field descriptions bit field type reset description 7-4 gpo2_seq r/w , e2 0h gpo2 enable strobe 0h = rail is not controlled by sequencer 1h = rail is not controlled by sequencer 2h = rail is not controlled by sequencer 3h = enable at strobe3 4h = enable at strobe4 5h = enable at strobe5 6h = enable at strobe6 7h = enable at strobe7 8h = enable at strobe8 9h = enable at strobe9 ah = enable at strobe10 bh = rail is not controlled by sequencer ch = rail is not controlled by sequencer dh = rail is not controlled by sequencer eh = rail is not controlled by sequencer fh = rail is not controlled by sequencer
80 TPS65216 slds187 ? october 2018 www.ti.com submit documentation feedback product folder links: TPS65216 detailed description copyright ? 2018, texas instruments incorporated table 4-33. seq7 register field descriptions (continued) bit field type reset description 3-0 gpo1_seq r/w , e2 3h gpo1 enable strobe 0h = rail is not controlled by sequencer 1h = rail is not controlled by sequencer 2h = rail is not controlled by sequencer 3h = enable at strobe3 4h = enable at strobe4 5h = enable at strobe5 6h = enable at strobe6 7h = enable at strobe7 8h = enable at strobe8 9h = enable at strobe9 ah = enable at strobe10 bh = rail is not controlled by sequencer ch = rail is not controlled by sequencer dh = rail is not controlled by sequencer eh = rail is not controlled by sequencer fh = rail is not controlled by sequencer
81 TPS65216 www.ti.com slds187 ? october 2018 submit documentation feedback product folder links: TPS65216 application and implementation copyright ? 2018, texas instruments incorporated 5 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 5.1 application information the TPS65216 is designed to pair with various application processors. the typical application in section 5.2 is based on and uses terminology consistent with the sitara ? family of processors.
82 TPS65216 slds187 ? october 2018 www.ti.com submit documentation feedback product folder links: TPS65216 application and implementation copyright ? 2018, texas instruments incorporated 5.2 typical application figure 5-1. typical application schematic TPS65216 ddr3/l memory 0.95/1.1v 0.95/1.1/1.2/1.26/1.325v nwakeup pwr_en pb scl/sda nint pgood 3.3v vdd_core vdd_mpu 3.3v analog & i/o 1.8v 1.8v analog & i/o 3.6-v to 5.5-v system power ac_det vddshv3 vddshvx for gpiox rtc_pmic_en pwronrstn rtc_wakeup 1.35/1.5v vdds_ddr in_dcdc1 in_dcdc2 in_dcdc3 in_dcdc4 in_ldo1 vddshv3 in_bias gpio2 ddr_resetn i2c0_scl/sda gpiox system power (5 v typical) ldo1 dcdc1 (buck) dcdc2 (buck) dcdc4 (buck-boost) dcdc3 (buck) digital bias push button copyright ? 2018, texas instruments incorporated
83 TPS65216 www.ti.com slds187 ? october 2018 submit documentation feedback product folder links: TPS65216 application and implementation copyright ? 2018, texas instruments incorporated 5.2.1 design requirements table 5-1 lists the design requirements. table 5-1. design parameters voltage sequence dcdc1 1.1 v 8 dcdc2 1.1 v 9 dcdc3 1.2 v 5 dcdc4 3.3 v 7 ldo1 1.8 v 3 5.2.2 detailed design procedure 5.2.2.1 output filter design the step down converters (dcdc1, dcdc2, and dcdc3) on TPS65216 are designed to operate with effective inductance values in the range of 1 to 2.2 h and with effective output capacitance in the range of 10 to 100 f. the internal compensation is optimized to operate with an output filter of l = 1.5 h and c out = 10 f. the buck boost converter (dcdc4) on TPS65216 is designed to operate with effective inductance values in the range of 1.2 to 2.2 h. the internal compensation is optimized to operate with an output filter of l = 1.5 h and c out = 47 f. larger or smaller inductor/capacitance values can be used to optimize performance of the device for specific operation conditions. 5.2.2.2 inductor selection for buck converters the inductor value affects its peak to peak ripple current, the pwm to pfm transition point, the output voltage ripple, and the efficiency. the selected inductor must be rated for its dc resistance and saturation current. the inductor ripple current ( ? l) decreases with higher inductance and increases with higher v in or v out . equation 1 calculates the maximum inductor current ripple under static load conditions. the saturation current of the inductor should be rated higher than the maximum inductor current as calculated with equation 2 . this is recommended as during heavy load transient the inductor current will rise above the calculated value. (1) where ? f = switching frequency ? l = inductor value ? ? i l = peak-to-peak inductor ripple current ? i lmax = maximum inductor current (2) the following inductors have been used with the (see table 5-2 ). table 5-2. list of recommended inductors part number value size (mm) [l w h] manufacturer inductors for dcdc1, dcdc2, dcdc3, dcdc4 l l max out max i i i 2 ' out in l out v v i v / | ' u u
84 TPS65216 slds187 ? october 2018 www.ti.com submit documentation feedback product folder links: TPS65216 application and implementation copyright ? 2018, texas instruments incorporated table 5-2. list of recommended inductors (continued) part number value size (mm) [l w h] manufacturer spm3012t-1r5m 1.5 h, 2.8 a, 77 m 3.2 3.0 1.2 tdk ihlp1212bzer1r5m11 1.5 h, 4.0 a, 28.5 m 3.6 3.0 2.0 vishay (1) the dc bias effect of ceramic capacitors must be considered when selecting a capacitor. 5.2.2.3 output capacitor selection the hysteretic pwm control scheme of the TPS65216 switching converters allows the use of tiny ceramic capacitors. ceramic capacitors with low esr values have the lowest output voltage ripple and are recommended. the output capacitor requires either an x7r or x5r dielectric. at light load currents the converter operates in power save mode, and the output voltage ripple is dependent on the output capacitor value and the pfm peak inductor current. higher output capacitor values minimize the voltage ripple in pfm mode and tighten dc output accuracy in pfm mode. the buck-boost converter requires additional output capacitance to help maintain converter stability during high load conditions. at least 40 f of output capacitance is recommended and an additional 100-nf capacitor can be added to further filter output ripple at higher frequencies. table 5-2 lists the recommended capacitors. table 5-3. list of recommended capacitors part number value size (mm) [l w h] manufacturer capacitors for voltages up to 5.5 v (1) grm188r60j105k 1 f 1608 / 0603 (1.6 0.8 0.8) murata grm21br60j475k 4.7 f 2012 / 0805 (2.0 1.25 1.25) murata grm31mr60j106k 10 f 3216 / 1206 (3.2 1.6 1.6) murata grm31cr60j226k 22 f 3216 / 1206 (3.2 1.6 1.6) murata 5.2.3 application curves at t j = 25 c unless otherwise noted v out = 1.1 v figure 5-2. dcdc1/dcdc2 efficiency v out = 1.2 v figure 5-3. dcdc3 efficiency output current (ma) efficiency 0 400.001 800.001 1200.001 1600.001 0 20% 40% 60% 80% 100% d007 v = 2.8 v in v in = 3.6 v v in = 5 v output current(a) efficiency 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 0 10% 20% 30% 40% 50% 60% 70% 80% 90% d008 v = 2.8 v in v in = 3.6 v v in = 5 v
85 TPS65216 www.ti.com slds187 ? october 2018 submit documentation feedback product folder links: TPS65216 layout copyright ? 2018, texas instruments incorporated at t j = 25 c unless otherwise noted v out = 1.5 v figure 5-4. dcdc3 efficiency v out = 3.3 v figure 5-5. dcdc4 efficiency 6 power supply recommendations the device is designed to operate with an input voltage supply range between 3.6 and 5.5 v. this input supply can be from an externally regulated supply. if the input supply is located more than a few inches from the TPS65216 additional bulk capacitance may be required in addition to the ceramic bypass capacitors. an electrolytic capacitor with a value of 47 f is a typical choice. 7 layout 7.1 layout guidelines follow these layout guidelines: ? the in_x pins should be bypassed to ground with a low esr ceramic bypass capacitor. the typical recommended bypass capacitance is 4.7- f with a x5r or x7r dielectric. ? the optimum placement is closest to the in_x pins of the device. take care to minimize the loop area formed by the bypass capacitor connection, the in_x pin, and the thermal pad of the device. ? the thermal pad should be tied to the pcb ground plane with a minimum of 25 vias. see figure 7-2 for an example. ? the lx trace should be kept on the pcb top layer and free of any vias. ? the fbx traces should be routed away from any potential noise source to avoid coupling. ? dcdc4 output capacitance should be placed immediately at the dcdc4 pin. excessive distance between the capacitance and dcdc4 pin may cause poor converter performance. 7.2 layout example output current (a) efficiency 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 0 10% 20% 30% 40% 50% 60% 70% 80% 90% d009 v = 2.8 v in v in = 3.6 v v in = 5 v output current (a) efficiency 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 0 20% 40% 60% 80% 100% d010 v = 2.7 v in v in = 3.6 v v in = 5 v
86 TPS65216 slds187 ? october 2018 www.ti.com submit documentation feedback product folder links: TPS65216 layout copyright ? 2018, texas instruments incorporated figure 7-1. layout recommendation figure 7-2. layout recommendation thermal pad fb1 l1 in via to ground plane via to internal plane input bypass capacitor output filter capacitor v out recommended thermal pad via size hole size (s) = 8 mil diameter (d) = 16 mil d s
87 TPS65216 www.ti.com slds187 ? october 2018 submit documentation feedback product folder links: TPS65216 device and documentation support copyright ? 2018, texas instruments incorporated 8 device and documentation support 8.1 device support 8.1.1 third-party products disclaimer ti's publication of information regarding third-party products or services does not constitute an endorsement regarding the suitability of such products or services or a warranty, representation or endorsement of such products or services, either alone or in combination with any ti product or service. 8.2 documentation support 8.2.1 related documentation for related documentation see the following: ? texas instruments, basic calculation of a buck converter ' s power stage application report ? texas instruments, design calculations for buck-boost converters application report ? texas instruments, empowering designs with power management ic (pmic) for processor applications application report ? texas instruments, tps65218evm user ' s guide ? texas instruments, tps65218 power management integrated circuit (pmic) for industrial applications application report 8.3 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 8.4 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community the ti engineer-to-engineer (e2e) community was created to foster collaboration among engineers. at e2e.ti.com , you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 8.5 trademarks sitara, e2e are trademarks of texas instruments.
88 TPS65216 slds187 ? october 2018 www.ti.com submit documentation feedback product folder links: TPS65216 mechanical, packaging, and orderable information copyright ? 2018, texas instruments incorporated 8.6 electrostatic discharge caution this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 8.7 glossary ti glossary this glossary lists and explains terms, acronyms, and definitions. 9 mechanical, packaging, and orderable information the following pages include mechanical packaging and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation.
copyright ? 2018, texas instruments incorporated mechanical, packaging, and orderable information submit documentation feedback product folder links: TPS65216 89 TPS65216 www.ti.com slds187 ? october 2018 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. pre_prod unannounced device, not in production, not available for mass market, nor on the web, samples not available. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. space (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti ' s terms " lead-free " or " pb-free " mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br) : ti defines " green " to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) space (3) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. space (4) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. space (5) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device space (6) multiple device markings will be inside parentheses. only on device marking contained in parentheses and separated by a " ~ " will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. important information and disclaimer: the information provided on this page represents ti ' s knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti ' s liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. 9.1 package option addendum 9.1.1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (3) msl peak temp (4) op temp ( c) device marking (5) (6) TPS65216d0rslr active vqfn rsl 48 2500 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 TPS65216d0 TPS65216d0rslt active vqfn rsl 48 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 TPS65216d0
90 TPS65216 slds187 ? october 2018 www.ti.com submit documentation feedback product folder links: TPS65216 mechanical, packaging, and orderable information copyright ? 2018, texas instruments incorporated 9.1.2 tape and reel information device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant TPS65216d0rslr vqfn rsl 48 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 q2 TPS65216d0rslt vqfn rsl 48 250 180.0 16.4 6.3 6.3 1.1 12.0 16.0 q2 reel width (w1) reel dimensions a0 b0k0 w dimension designed to accommodate the component lengthdimension designed to accommodate the component thickness overall width of the carrier tape pitch between successive cavity centers dimension designed to accommodate the component width tape dimensions k0 p1 b0 w a0 cavity quadrant assignments for pin 1 orientation in tape pocket quadrants sprocket holes q1 q1 q2 q2 q3 q3 q4 q4 reel diameter user direction of feed p1
91 TPS65216 www.ti.com slds187 ? october 2018 submit documentation feedback product folder links: TPS65216 mechanical, packaging, and orderable information copyright ? 2018, texas instruments incorporated device package type package drawing pins spq length (mm) width (mm) height (mm) TPS65216d0rslr vqfn rsl 48 2500 367.0 367.0 38.0 TPS65216d0rslt vqfn rsl 48 250 210.0 185.0 35.0 tape and reel box dimensions width (mm) w l h
package option addendum www.ti.com 17-oct-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples TPS65216d0rslr preview vqfn rsl 48 2500 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 t65216d0 TPS65216d0rslt preview vqfn rsl 48 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 t65216d0 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
package option addendum www.ti.com 17-oct-2018 addendum-page 2
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant TPS65216d0rslr vqfn rsl 48 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 q2 TPS65216d0rslt vqfn rsl 48 250 180.0 16.4 6.3 6.3 1.1 12.0 16.0 q2 package materials information www.ti.com 17-oct-2018 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) TPS65216d0rslr vqfn rsl 48 2500 367.0 367.0 38.0 TPS65216d0rslt vqfn rsl 48 250 210.0 185.0 35.0 package materials information www.ti.com 17-oct-2018 pack materials-page 2

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